Sequential Circuits – GATE ECE Digital CircuitsPractice Questions & PYQs

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input P0 is set to logic '0' and P1 is set to logic '1' at all times. The timing diagram of the inputs SEL and S are also shown below. The sequence of output Y from time $\mathrm{T}_{0}$ to $\mathrm{T}_{3}$ is __________ .

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flipflops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is __________ .

The sequence of states $\left(Q_{1} Q_{0}\right)$ of the given synchronous sequential circuit is ______

The synchronous sequential circuit shown below works at a clock frequency of $1 \mathrm{GHz}$ . The throughput, in $\mathrm{M}$ bits/s, and the latency, in ns, respectively, are

In a given sequential circuit, initial states are $Q_{1}=1$ and $Q_{2}=0$ . For a clock frequency of $1 \mathrm{MHz}$ , the frequency of signal $Q_{2}$ in $\mathrm{kHz}$ , is ____ (rounded off to the nearest integer).

For the circuit shown, the clock frequency is $f_o$ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, _______.

A state transition diagram with states A, B, and C, and transition probabilities $p_1,p_2,...,p_7$ is shown in the figure (e.g., $p_1$ denotes the probability of transition from state A to B). For this state diagram, select the statement(s) which is/are universally true

The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is

The propagation delay of the exclusive $-\text{OR} (\text{XOR})$ gate in the circuit in the figure is $3\:ns$ . The propagation delay of all the flip-flops is assumed to be zero. The clock $(\text{Clk})$ frequency provided to the circuit is $500\: \text{MHz}$ . Starting from the initial value of the flip-flop outputs $Q_{2}Q_{1}Q_{0} = 1\;1\;1$ with $D_{2}=1$ , the minimum number of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is

For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{setup}$ is the setup time, and $t_{hold}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is ____ MHz.

The state diagram of a sequence detector is shown below. State $S_0$ is the initial state of the sequence detector. If the output is 1, then

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12?kHz. The frequency of the signal at $Q_2$ is____ kHz.

A 4-bit shift register circuit configured for right-shift operation, i.e, $D_{\in}\rightarrow A,\; A\rightarrow B , \; B\rightarrow C, \; C\rightarrow D$ , as shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = '0'. If the input condition is changed simultaneously to P = Q = '1', the outputs X and Y are

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is___________.

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R= 10 k $\Omega$ and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle. The average power dissipated (in mW) in the resistor R is ________

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero. If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is _______.

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ( $\bar{R_{d}}$ input).The counter corresponding to this circuit is (