Q2GATE 2024MCQ

The propagation delay of the $2 \times 1 \mathrm{MUX}$ shown in the circuit is $10 \mathrm{~ns}$ . Consider the propagation delay of the inverter as $0 \mathrm{~ns}$ . If $S$ is set to 1 then the output $Y$ is ______

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📖 Explanation

\begin{array}{ll} \therefore & T_{c}=10+10=20 \mathrm{nsec} \\ \therefore & f_{c}=\frac{1}{T_{C}}=\frac{10^{9}}{20}=50 \mathrm{MHz} \end{array}

Q3GATE 2023MCQ

In the circuit shown below, $P$ and $Q$ are the inputs. The logical function realized by the circuit shown below is

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📖 Explanation

\begin{aligned} \text { Output } & =\bar{Q} \cdot I_{0}+Q \cdot I_{1} \\ & =\bar{Q} \cdot 0+Q \cdot P \\ & =P Q \end{aligned}

Q4GATE 2022MCQ

Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for $A_0,A_1,A_2 \text{ and }A_3$ are _______

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📖 Explanation

$f=\bar{C}\bar{D}I_0+\bar{C}DI_1+C\bar{D}I_2+CDI_3$ For this $A_0=A_3=0$ $A_1=A_2=1$

Q5GATE 2020MCQ

The figure below shows a multiplexer where $S_1 \; and \; S_0$ are the select lines, $I_0 \; to \; I_3$ are the input data lines, EN is the enable line, and $F(P, Q, R)$ is the output, F is

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📖 Explanation

Output, $F=\bar{P}\bar{Q}R+P\bar{Q}R+PQ\, \, \, \,$ $F=\bar{Q}R+PQ$

Q6GATE 2018MCQ

A four-variable Boolean function is realized using 4x1 multiplexers as shown in the figure. The minimized expression for F(U,V,W, X) is

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📖 Explanation

Output of the first multiplexer can be expressed as, $F_{1}=\bar{U} V+U \bar{V}$ Output of the second multiplexer can be expressed as,

\begin{aligned} F &=\bar{W} \bar{X} F_{1}+\bar{W} X F_{1}=\bar{W} F_{1} \\ &=(\bar{U} V+U \bar{V}) \bar{W} \end{aligned}

Q7GATE 2017NAT

Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to At t=0, the inputs to the 4-bit adder are changed to $X_{3}X_{2}X_{1}X_{0}=1100,\; Y_{3}Y_{2}Y_{1}Y_{0}=0100 \; and \; Z_{0}=1$ . The output of the ripple carry adder will be stable at t (in ns) = ___________

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📖 Explanation

In this question inputs to be added are :

\begin{aligned} X_{3} X_{2} X_{1} X_{0}&=1100 \\ Y_{3} Y_{2} Y_{1} Y_{0}&=0100 \text { and } Z_{0}=1 \end{aligned}

For this combination of addition, total minimum delay depends on the addition of most-significant two bits (since least significant two bits are zeros they does not cause any change in $Z_{1}$ and $Z_{2}$ ). So, in the process of addition of given two digits, waveforms at $Z_{1}$ and $Z_{2}$ become stable at t=0 itself. In the above diagram the waveform at A and B become stable at t = 0 itself, as the applied input combinations does not cause any change. So, for he given combination of inputs, output will settle at t = 50 ns.

Q8GATE 2017MCQ

A programmable logic array (PLA) is shown in the figure. The Boolean function F implemented is

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📖 Explanation

$F=\bar{P} \bar{Q} R+\bar{P} Q R+P \bar{Q} R$

Q9GATE 2017MCQ

Consider the circuit shown in the figure. The Boolean expression F implemented by the circuit is

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📖 Explanation

\begin{aligned} F_{1} &=\bar{X} Y \\ F &=\bar{Z} F_{1}+Z \bar{F}_{1} \\ &=(\bar{X} Y) \bar{Z}+(\bar{X} Y) Z \\ &=\bar{X} Y \bar{Z}+(X+\bar{Y}) Z \\ F &=\bar{X} Y \bar{Z}+X Z+\bar{Y} Z \end{aligned}

Q10GATE 2016MCQ

Identify the circuit below.

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📖 Explanation

The truth table of the circuit is shown below,

\begin{array}{ccc|ccc} X_{2} & X_{1} & X_{0} & Y_{2} & Y_{1} & Y_{0} \\ \hline 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 1 \\ 0 & 1 & 0 & 0 & 1 & 1 \\ 0 & 1 & 1 & 0 & 1 & 0 \\ 1 & 0 & 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 0 & 0 \\ 1 & 1 & 1 & 1 & 0 & 1 \end{array}

As Per the truth table none of the options given in the question are correct. However, by making some (minor) changes in the circuit, the answer could be obtained as option (A). As per GATE official answer Marks to ALL.

Q11GATE 2016MCQ

A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while $C_{\in}$ is the input carry and $C_{out}$ is the output carry. A and B are to be used as the select bits with A being the more significant select bit. Which one of the following statements correctly describes the choice of signals to be connected to the inputs $I_{0},I_{1},I_{2} \; and \; I_{3}$ so that the output is $C_{out}$ ?

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📖 Explanation

In case of a full adder,

\begin{aligned} \therefore \quad I_{0}&=0 \\ I_{1}&=C_{\text {\in }} \\ I_{2}&=C_{\text {\in }} \\ I_{3}&=1 \end{aligned}

Q12GATE 2016NAT

For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is __________

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📖 Explanation

When, $T=\text{logic} 0$ , the path followed by the circuit would be, NOR gate $\rightarrow \text{MUX} 1 \rightarrow \text{MUX} 2$ $\Rightarrow 2 \mathrm{ns} \rightarrow 1.5 \mathrm{ns} \rightarrow 1.5 \mathrm{ns}$ $\Rightarrow 5 \mathrm{ns}$ When, $T=\text{logic} 1$ , the path followed by the circuit would be, NOR gate $\rightarrow MUX 1 \rightarrow NOR gate \rightarrow MUX 2$ $\Rightarrow 1 \mathrm{ns} \rightarrow 1.5 \mathrm{ns} \rightarrow 2 \mathrm{ns} \rightarrow 1.5 \mathrm{ns}$ $\Rightarrow 6 \mathrm{ns}$ $\therefore \quad$ Maximum propagation delay is 6 ns

Q13GATE 2015MCQ

A 1-to-8 demultiplexer with data input $D_{\in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\bar{Y}_{0} \; to \; \bar{Y}_7$ as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable E input and address inputs $A_{0} \; and \; A_{1}$ ) as shown in the figure. $D_{\in} , S_{0}, S_{1} \; and \; S_{2}$ are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be

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📖 Explanation

Consider a $1 \times 8$ demultiplexer

\begin{aligned} \text{So,}\quad \bar{Y}_{0} &=\left(\overline{D_{\text {\in }} \cdot \bar{S}_{0} \bar{S}_{1} \bar{S}_{2}}\right) \\ \bar{Y}_{0} &=\left(\bar{D}_{\text {\in }}+S_{0}+S_{1}+S_{2}\right) \\ \bar{Y}_{1} &=\left(\bar{D}_{\text {\in }}+\bar{S}_{0}+S_{1}+S_{2}\right) \\ \bar{Y}_{2} &=\left(\bar{D}_{\text {\in }}+S_{0}+\bar{S}_{1}+S_{2}\right) \\ \bar{Y}_{3} &=\left(\bar{D}_{\text {\in }}+\bar{S}_{0}+\bar{S}_{1}+S_{2}\right) \\ \bar{Y}_{4} &=\left(\bar{D}_{\text {\in }}+S_{0}+S_{1}+\bar{S}_{2}\right) \\ \bar{Y}_{5} &=\left(\bar{D}_{\text {\in }}+\bar{S}_{0}+S_{1}+\bar{S}_{2}\right) \\ \bar{Y}_{6} &=\left(\bar{D}_{\text {\in }}+S_{0}+\bar{S}_{1}+\bar{S}_{2}\right) \\ \bar{Y}_{7} &=\left(\bar{D}_{\text {\in }}+S_{0}+S_{1}+S_{2}\right) \end{aligned}

From the circuit given in question we can see that

\begin{array}{l} \bar{Y}_{0}=\left(1 A_{0}+1 A_{1}+\bar{E}\right) \\ \bar{Y}_{0}=(R+S+P+Q) \end{array}

Similarly, $\bar{Y}_{1}=\left(1 \bar{A}_{0}+1 A_{1}+1 \bar{E}\right)=(P+Q+\bar{R}+S)$ $\bar{Y}_{4}=\left(2 \bar{A}_{0}+2 A_{1}+2 \bar{E}\right)=(R+S+P+\bar{Q})$ So comparing, we get

\begin{array}{l} P={D}_{\text {\in }} \\ Q=S_{2} \\ R=S_{1} \\ S=S_{0} \end{array}

Q14GATE 2014MCQ

In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by

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📖 Explanation

For the state equation of 4: 1 MUX, we know that

\begin{aligned} A &=\bar{W} \bar{X}_{I_{0}}+\bar{W} X_{I_{1}+W \bar{X}_{I_{2}}+W X_{I_{3}}} \\ &=\bar{W} X+W \bar{X} & \text { (since }\left.V_{C C}=1\right) \end{aligned}

Now, output F

\begin{aligned} &=\bar{Y} \bar{Z} I_{0}+\bar{Y} Z I_{1}+Y \bar{Z} I_{2}+Y Z I_{3}\\ &=\bar{W} X\bar{Y} \bar{Z}+W \bar{X} \bar{Y} \bar{Z}+\bar{W} \times \nabla Z+W \bar{X} \bar{Y} Z \\ &=\bar{W} X \bar{Y}(\bar{Z}+Z)+W \bar{X} \bar{Y}(\bar{Z}+Z) \\ &=W \bar{X} \bar{Y}+\bar{W} X \bar{Y} \end{aligned}

Q15GATE 2014MCQ

An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by

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📖 Explanation

Depending upon the select lines one input is transferred to the output in multiplexer.

\begin{aligned} \therefore \quad Y &=\bar{A} \bar{B} C D+\bar{A} B C D+A B \bar{C} \\ &=\bar{A} C D(\bar{B}+B)+A B \bar{C} \\ &=A B \bar{C}+ \bar{A} C D \end{aligned}

Q16GATE 2014MCQ

Consider the multiplexer based logic circuit shown in the figure. Which one of the following Boolean functions is realized by the circuit ?

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📖 Explanation

Using the state equation of the multiplexer, we get

\begin{aligned} X&=\bar{S}_{1} \cdot W+S_{1} \bar{W}\\ \text{So, }\quad F&=\bar{S}_{2} \cdot X+S_{2} \bar{X} \\ &=\bar{S}_{2}\left(\bar{S}_{1} W+S_{1} \bar{W}\right)+S_{2}(\overline{\bar{S}_{1} W+S_{1} \bar{W}}) \\ &=\bar{S}_{1} \bar{S}_{2} W+S_{1} \bar{S}_{2} \bar{W}+S_{2} \bar{S}_{1} \bar{W}+S_{2} S_{1} W \\ F&=W \oplus S_{1} \oplus S_{2} \end{aligned}

Q17GATE 2014MCQ

In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N=X-Y) are given by

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📖 Explanation

\begin{array}{llcl} X & Y & N=X-Y & M \\ 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 0 \\ 1 & 1 & 0 & 0 \\ \end{array}

$N= X \oplus Y, M= \bar{X} Y$

Q18GATE 2014MCQ

If X and Y are inputs and the Difference (D=X-Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor ?

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📖 Explanation

\begin{array}{cccc} X & Y& D& B \\ 0 & 0&0&0 \\ 0 & 1&1&1 \\ 1 & 0&1&0 \\ 1 & 1&0&0 \\ \end{array}

$\therefore \text { Difference }=\bar{X} Y+X \bar{Y}=X \oplus Y$ Borrow $=\bar{X} Y$ Also using the state equation of MUX if X is used as a select line and Y as input, we get

\begin{array}{l} D=\bar{X} Y+X \bar{Y} \\ B=\bar{X} Y \end{array}

option (a) satisfies

Q19GATE 2014NAT

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sumpropagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be ______.

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📖 Explanation

Full adder is a combinational circuit that performs the sum of three bits i.e. add two bits and a carry from previous addition and produces output as sum and carry. Given carry propagation delay of each $FA= 12\mathrm{nsec}.$ Sum-propagation delay of each $FA= 15\mathrm{nsec}.$ As can be seen from above diagram, full adder is not received from previous full adder. So, in 16-bit ripple carry adder, worst case delay of this 16-bit adder will be

\begin{aligned} &= (15 \times 12) \mathrm{nsec}. + 15 \mathrm{nsec}.\\ &= 195 \mathrm{nsec}. \end{aligned}

Q20GATE 2012MCQ

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

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