Logic Families Practice Questions

In the circuits shown, the threshold voltage of each Nmos transistor is 0.6 V. Ignoring the effect of channel length modulation and body bias, the values of Vout1 and Vout2, respectively, in volts, are

In the circuit shown, A and B are the inputs and Fis the output. What is the functionality of the circuit?

In the circuit shown, what are the values of F for EN=0 and EN=1, respectively?

A standard CMOS inverter is designed with equal rise and fall times ( $\beta _n=\beta _p$ ). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin ( $NM_L$ ) and the HIGH noise margin $NM_H$ ?

The logic function f(X,Y) realized by the given circuit is

The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement "wired logic". Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH. The number of distinct values of $X_{3}X_{2}X_{1}X_{0}$ (out of the 16 possible values) that give Y = 1 is _______.

For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is

The functionality implemented by the circuit below is

The logic functionality realized by the circuit shown below is

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

In the circuit shown, diodes $D_{1} , D_{2} \; and \; D_{3}$ are ideal, and the inputs $E_{1} , E_{2} \; and \; E_{3}$ are "0 V" for logic '0' and "10 V" for logic '1'. What logic gate does the circuit represent?

In the following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1V. Ignoring the body-effect, the output voltages at P, Q and R are,

The output (Y ) of the circuit shown in the figure is

In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is +5 V, X and Y are digital signals with 0 V as logic 0 and $V_{cc}$ as logic 1, then the Boolean expression for Z is

In the circuit shown

The full form of the abbreviations TTL and CMOS in reference to logic families are

The logic function implemented by the following circuit at the terminal OUT is

The circuit diagram of a standard TTL NOT gate is shown in the figure. $V_i = 2.5 V$ , the modes of operation of the transistors will be

The transistors used in a portion of the TTL gate show in the figure have $\beta$ = 100. The base emitter voltage of is 0.7 V for a transistor in active region and 0.75 V for a transistor in saturation. If the sink current I = 1mA and the output is at logic 0, then the current $I_{R}$ will be equal to