Q1GATE 2023NAT

For the circuit shown below, the propagation delay of each NAND gate is $1 \mathrm{~ns}$ . The critical path delay, in ns, is ____ (rounded off to the nearest integer).

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📖 Explanation

The given circuit can be drawn as; $\therefore \quad$ The critical path delay $=1 \mathrm{~ns}+1 \mathrm{~ns}=2 \mathrm{~ns}$

Q2GATE 2022MSQ

Consider a Boolean gate (D) where the output $Y$ is related to the inputs $A$ and $B$ as, $Y=A+\bar{B}$ , where + denotes logical OR operation. The Boolean inputs '0' and '1' are also available separately. Using instances of only D gates and inputs '0' and '1', __________ (select the correct option(s)).

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📖 Explanation

\begin{aligned} y &=A+\bar{B} =\overline{\bar{A}\cdot B}\\ f(A,B)&=A+\bar{B} \\ f(0,B) &=0+\bar{B}=\bar{B}\Rightarrow NOT\; Gate \\ f(A,\bar{B}) &=A+\bar{\bar{B}} =A+B\Rightarrow OR \;Gate\\ f(0,f(A,\bar{B}))&=0+(\overline{A+B})\Rightarrow NOR \; Gate \\ f(\bar{A},B) &= \bar{A}+\bar{B}=\overline{A\cdot B}\Rightarrow NAND\; Gate\\ f(0,f(\bar{A},B))&=0+\overline{\overline{A\cdot B}} =A\cdot B\Rightarrow AND \; Gate \end{aligned}

Since, we can implement NOT Gate we can also implement OR, AND, NOR and NAND Gate.

Q3GATE 2016MCQ

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

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Q4GATE 2016MCQ

The output of the combinational circuit given below is

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📖 Explanation

\begin{aligned} y &=A B C \oplus A B \oplus B C \\ &=[\overline{A B C} \cdot A B+A B C \cdot \overline{A B}] \oplus B C \\ &=[(\bar{A}+\bar{B}+\bar{C}) \cdot A B+A B C \cdot(\bar{A}+\bar{B})] \oplus B C \\ &=(A B \bar{C}) \oplus(B C) \\ &=\overline{A B \bar{C}} \cdot B C+A B \bar{C} \cdot \overline{B C} \\ &=(\bar{A}+\bar{B}+C) \cdot B C+A B \bar{C} \cdot(\vec{B}+\bar{C}) \\ &=\bar{A} B C+B C+A B \bar{C} \\ &=B C(\bar{A}+1)+A B \bar{C}=B C+A B \bar{C} \\ &=B(C+A \bar{C})=B(C+A) \end{aligned}

Q5GATE 2015MCQ

A 3-input majority gate is defined by the logic function M(a,b,c) = ab + bc + ca . Which one of the following gates is represented by the function $M(M\overline{(a,b,c)},M(a,b,\bar{c}),c)$ ?

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📖 Explanation

\begin{aligned} M(a, b, c) &=a b+b c+c a \\ \overline{M(a, b, c)} &=\frac{a b+b c+c a}{a b \cdot b c} \cdot \overline{c a} \\ &=(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a}) \\ M(a, b, \bar{c}) &=a b+b \bar{c}+\bar{c} a \end{aligned}

\begin{array}{l} \begin{aligned} M(\overline{M(a, b, c)}, M(a, b, \bar{c}) c) &=\\ \left[\begin{array}{l}(\overline{a b} \cdot \overline{b c} \cdot \overline{c a})(a b+b \bar{c}+\overline{c a}) \\ +(a b+b \bar{c}+\bar{c} a)(c)+(\overline{a b} \cdot \overline{b c} \cdot \bar{a} a \mid)\end{array}\right]\end{aligned} \\ =\left[\begin{array}{l} (\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})(a b+b \bar{c}+\bar{c} a) \\ +a b c+(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a}) c \end{array}\right] \\ =(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})[a b+b \bar{c}+\bar{c} a+c]+a b c \\ =(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})[a+b+c]+a b c \\ =(\bar{a} \bar{b}+\bar{b} \bar{c}+\bar{c} \bar{a})[a+b+c]+a b c \\ F=a \bar{b} \bar{c}+b \bar{c} \bar{a}+c \bar{a} \bar{b}+a b c \\ F=A \oplus B \oplus C \end{array}

Q6GATE 2015MCQ

In the figure shown, the output Y is required to be $Y=AB+\bar{C}\bar{D}$ .The gates G1 and G2 must be, respectively,

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📖 Explanation

\begin{aligned} Y &=A B+\bar{C} \bar{D} \\ G_1 &=\text { NOR Gate } \quad \bar{A} \text{ NOR } \bar{B}=A B \\ G 2 &=\text { OR GATE } \quad A B+\bar{C} \bar{D} \end{aligned}

Q7GATE 2015NAT

All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1 until time t = 0. At t = 0, all the inputs flip (i.e., A = C = 1 and B = 0) and remain in that state. For t > 0, output Z = 1 for a duration (in ns) of ______________.

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Q8GATE 2015MCQ

A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE?

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Q9GATE 2014MCQ

In the circuit shown in the figure, if C = 0, the expression for Y is

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📖 Explanation

Output of gate $1: \bar{C}$ Output of gate $2: \rightarrow(\overline{A+B})$ Output of gate $3: \rightarrow(\overline{A+B}+C)$ Output of gate $4: \rightarrow AB$ Output of gate $5: \rightarrow(\overline{A+B}+C)+A B$ Output of gate 6 is output Y i.e.

\begin{aligned} Y &=\overline{\bar{C} \cdot(\overline{A+B}+C)+A B} \\ &=C+\overline{(\overline{A+B}+C+A B)} \end{aligned}

Using Demorgan's theorem

\begin{aligned} &=C+(\overline{\overline{A+B}}) \cdot \bar{C} \cdot(\overline{A B})\\ &=C+(A+B) \cdot \bar{C} \cdot(\bar{A}+\bar{B}) \end{aligned}

Given in question C=0

\begin{aligned} \text{So, }Y&=0+(A+B) \cdot \overline{0} \cdot(\bar{A}+\bar{B}) \\ &=\bar{A} B+A \bar{B} \end{aligned}

Q10GATE 2014MCQ

The output F in the digital logic circuit shown in the figure is

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📖 Explanation

\begin{aligned} A &=X \oplus Y \\ B &=A \odot Z=A \cdot Z+\bar{A} \bar{Z} \\ &=Z(X \oplus Y)+(X \odot Y) \bar{Z} \\ F &=A B \\ &=(X \oplus Y)[Z(X \oplus Y)+\bar{Z}(\overline{X \oplus Y})] \\ &=Z[(X \oplus Y)(X \oplus Y)+\bar{A}(\overline{X \oplus Y})(X \oplus Y)] \\ &\begin{aligned} \text { as we know } A \cdot A &=A \\ A \cdot \bar{A} &=0 \\ &=Z[(X \oplus Y)+0] \\ &=\bar{X} Y Z+X \bar{Y} Z \end{aligned} \end{aligned}

Q11GATE 2013MCQ

A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles

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📖 Explanation

Truth table of XOR gate

\begin{array}{cc|c} A & B & Y \\ \hline 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \end{array}

So, from the XOR gate truth table it is clear that the bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch.

Q12GATE 2011MCQ

The output Y in the circuit below is always '1' when

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📖 Explanation

$Y= PO+ PR+ RO$

Q13GATE 2010MCQ

Match the logic gates in Column A with their equivalents in Column B

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📖 Explanation

NOR gate is equivalent to INVERT -AND gate. NANO gate is equivalent to INVERT - OR gate.

\begin{array}{c} F=X \bar{Y}+\bar{X} Y \\ F=\bar{X} Y+\bar{\bar{X}} \bar{Y} \\ F=\bar{X}Y+X\bar{Y} \\ F=X Y+\bar{X} \bar{Y} \\ F=X \bar{\bar{Y}}+\bar{X} \bar{Y}\\ F=XX+\bar{X}\bar{Y} \end{array}

Q14GATE 2010MCQ

For the output F to be 1 in the logic circuit shown, the input combination should be

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📖 Explanation

\begin{aligned} \text{If }\quad A&=0, B=0 \text{ then}\\ X&=\bar{A} B+A \bar{B}=0 \\ Y&=A B+\bar{A} \bar{B}=1 \end{aligned}

F will be '1' if even number of inputs to final XNOR gate is '1'; Hence, option (D) is the correct answer.

Q15GATE 2008MCQ

Which of the following Boolean Expressions correctly represents the relation between P,Q,R and $M_{1}$

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📖 Explanation

\begin{aligned} M_{1} &=[\overline{P Q}(P+Q)] \oplus R \\ &=[(\bar{P}+\bar{Q})(P+Q)] \oplus R \\ &=(P \oplus Q) \oplus R \end{aligned}

Q16GATE 2006MCQ

The number of product terms in the minimized sum-of-product expression obtained through the following K - map is (where, "d" denotes don't care states)

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Q17GATE 2004MCQ

A Boolean function f of two variables x and y is defined as follows : f (0,0) = f (0,1) = f (1,1) = 1; f (1,0) = 0 Assuming complements of x and y are not available, a minimum cost solution for realizing f using only 2-input NOR gates and 2-input OR gates (each having unit cost) would have a total cost of

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📖 Explanation

\begin{array}{lll} x & y & f \\ 0 & 0 & 1 \\ 0 & 1 & 1 \\ 1 & 0 & 0 \\ 1 & 1 & 1 \end{array}

Since complements are not available $\therefore$ 2 units

Q18GATE 2002MCQ

If the input to the digital circuit (shown in figure ) consisting of a cascade of 20 XOR gates is X, then the output Y is equal to

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📖 Explanation

\begin{array}{l} \text { Output of } 1 \mathrm{st} \text { XOR gate }=\bar{X} \\ \text { Output of } 2 \text { nd } \mathrm{XOR} \text { gate }=\bar{X} \oplus X \\ =(\bar{X}) \cdot X+\bar{X} \cdot \bar{X}=X+\bar{X}=1 \end{array}

Output of 20 XOR gates is 1

Q19GATE 2002MCQ

The gates G1 and G2 in figure have propagation delays of 10 nsec and 20 nsec respectively. If the input $V_{i}$ makes an abrupt change from logic 0 to 1 at time $t=t_{0}$ then the output waveform $V_{0}$ is

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Q20GATE 2001MCQ

In figure, the LED

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📖 Explanation

For LED to be ON, output of NANO gate = 0 No condition of $S_{1}$ and $S_{2}$ gives output of NANO gate zero. So LED will never glow

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