GATE ECE · Digital Circuits

Adc And Dac – GATE ECE Digital CircuitsPractice Questions & PYQs

Generate GATE-level questions on ADC and DAC. Focus on: 1. DAC types: Weighted resistor and R-2R ladder. 2. ADC types: Flash, Successive approximation, Dual-slope, and Ramp. 3. Performance metrics: Resolution, quantization error, and conversion time.

16 questions · 16 PYQs · 0 AI practice · GATE ECE 2027

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Q1GATE 2025NAT

A 4-bit weighted-resistor DAC with inputs $\mathrm{b}_{3}, \mathrm{~b}_{2}$ , $\mathrm{b}_{1}$ , and $\mathrm{b}_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic '1' and open otherwise. When the input $\mathrm{b}_{3} \mathrm{~b}_{2} \mathrm{~b}_{1} \mathrm{~b}_{0}$ changes from 1110 to 1101, the magnitude of the change in the output voltage $\mathrm{V}_{\mathrm{O}}$ (in mV , rounded off to the nearest integer) is __________ .

🚀 Solve in Practice Mode

📖 Explanation

$V_{0}=-R\left(\frac{b_{3} V_{R E F}}{R}+\frac{b_{2} V_{R E F}}{2 R}+\frac{b_{1} V_{R E F}}{4 R}+\frac{b_{0} V_{R E F}}{8 R}\right)$ $=-\frac{\mathrm{V}_{\text {REF }} \times \mathrm{R}}{\mathrm{R}}\left[\mathrm{b}_{3}+\frac{\mathrm{b}_{2}}{2}+\frac{\mathrm{b}_{1}}{4}+\frac{\mathrm{b}_{0}}{8}\right]$ $=-V_{\text {REF }}\left[\mathrm{b}_{3}+\frac{\mathrm{b}_{2}}{2}+\frac{\mathrm{b}_{1}}{4}+\frac{\mathrm{b}_{0}}{8}\right]$ For the input $\mathrm{b}_{3} \mathrm{~b}_{2} \mathrm{~b}_{1} \mathrm{~b}_{0}=1110$ , the output voltage,

\begin{aligned} \mathrm{V}_{0} & =-2\left(1+\frac{1}{2}+\frac{1}{4}+0\right) \\ & =-2(1.75) \\ & =-3.5 \mathrm{~V} \end{aligned}

For the input $\mathrm{b}_{3} \mathrm{~b}_{2} \mathrm{~b}_{1} \mathrm{~b}_{0}=1101$ , the output voltage,

\begin{aligned} \mathrm{V}_{0} & =-2\left(1+\frac{1}{2}+0+\frac{1}{8}\right) \\ & =-2(1.625) \\ & =-3.25 \mathrm{~V} \end{aligned}

So, the change in magnitude is 0.25 V and it is equal to 250 mV.

Q2GATE 2025MCQ

A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V. For an input sinusoidal signal with frequency 500 kHz , the maximum SNR (in dB , rounded off to two decimal places) and the data rate (in Mbps) at the output of the ADC are __________ , respectively.

🚀 Solve in Practice Mode

📖 Explanation

The maximum SNR for n bit $=6.02 \times \mathrm{n}+1.76 \mathrm{~dB}$ For 10 bits $=6.02 \times 10+1.76 \mathrm{~dB}=61.96 \mathrm{~dB}$ The sampling frequency is 1 MHz and each sample is converted into 10 bits. So, the data rate at the output $=10 \times 1 \mathrm{M}$ bits per second $=10 \mathrm{Mbps}$

Q3GATE 2024MCQ

A full scale sinusoidal signal is applied to a 10-bit ADC. The fundamental signal component in the ADC output has a normalized power of $1 \mathrm{~W}$ , and the total noise and distortion normalized power is $10 \mu \mathrm{W}$ . The effective number of bits (rounded off to the nearest integer) of the ADC is ____

🚀 Solve in Practice Mode

📖 Explanation

\begin{aligned} \frac{S}{N_{q}} & =\frac{1}{10 \times 10^{-6}} \\ \frac{S}{N_{q}} & =10^{5} \\ \left(\frac{S}{N_{a}}\right)_{\mathrm{dB}} & =10 \log _{10} 10^{5} \\ & =50 \mathrm{~dB} \\ 1.76+6.02 n & =50 \\ n & =8.01 \end{aligned}

rounded off to nearest integer $\rightarrow n \simeq 8$

Q4GATE 2022NAT

Consider the circuit shown with an ideal OPAMP. The output voltage $V_o$ is __________V (rounded off to two decimal places).

🚀 Solve in Practice Mode

📖 Explanation

$V_A=\frac{V_R}{2} \; and R_{th}=R$ $V_B=\frac{V_B}{2}$ $V_C=\frac{(V_R+V_R/4)}{2}=\frac{5}{8}V_R$ $R_{th}=2R||2R=R$ Similarly, $V_D=\frac{V_C}{2}=\frac{5}{16}V_R$ So, $\frac{S}{16}V_R=\frac{5}{16} \times 1.6V$ $V_o=\frac{-3R}{(2R+R)} \times \frac{5}{16} \times 1.6=-\frac{3}{2} \times \frac{5}{16} \times 1.6$ $V_o=-0.5V$

Explanation Figure 2

Explanation Figure 3

Q5GATE 2021NAT

An 8-bit unipolar (all analog output values are positive) digital-to-analog converter (DAC) has a full-scale voltage range from $0\; V$ to $7.68\:V$ . If the digital input code is $10010110$ (the leftmost bit is $\text{MSB}$ ), then the analog output voltage of the DAC (rounded off to one decimal place) is ___________ V.

🚀 Solve in Practice Mode

📖 Explanation

\begin{aligned} \text { Given: } \qquad \qquad V_{p s}&=7.68 \mathrm{~V} \\ n &=8 \mathrm{bit} \\ \text { Resolution }(k) &=\frac{V_{F S}}{2^{n}-1}=\frac{7.68}{2^{8}-1}=0.03\\ \text { Now, } \quad V_{\mathrm{DAC}}&=k \times \{\text { Decimal equivalent }\}\\ &=0.03 \times \{150\} \\ &=4.5 \mathrm{~V} \end{aligned}

Q6GATE 2020NAT

A 10-bit D/A converter is calibrated over the full range from 0 to 10 V. If the input to the D/A converter is 13A (in hex), the output (rounded off to three decimal places) is _________ V.

🚀 Solve in Practice Mode

📖 Explanation

Given, n=10 $V_{FS}=10\, V$ Input Voltage= $(13A)_{16}=(314)_{10}$ Output Voltage=Resolution X Decimal Equivalent of input $V_{o}=\frac{10}{2^{10}-1}\times 314=3.069\, V$

Q7GATE 2016MCQ

In an N bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{\in}$ (whose output is being converted to digital format) has a source resistance of 75 $\Omega$ as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale input change for proper conversion. Assume that the time taken by the thermometer to binary encoder is negligible. If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate ?

🚀 Solve in Practice Mode

📖 Explanation

In an 8-bit flash ADC, there are $2^8 - 1 = 255$ comparators. Each comparator has an input capacitance $C = 8 \text{ pF}$ . Total capacitance $C_{total} = 255 \times 8 \text{ pF} \approx 2040 \text{ pF} = 2.04 \text{ nF}$ . The source resistance $R = 75 \Omega$ . The time constant $\tau = RC = 75 \times 2.04 \text{ nF} = 153 \text{ ns}$ . For 8-bit accuracy within $\frac{1}{2}$ LSB, the input must settle to $\frac{1}{2^{8+1}} = \frac{1}{512}$ of the full-scale value. This requires a settling time $t_s \approx \tau \ln(512) \approx 6.24\tau = 6.24 \times 153 \text{ ns} \approx 955 \text{ ns} \approx 1 \mu\text{s}$ . The maximum sampling rate is thus $f_s = \frac{1}{t_s} \approx 1 \text{ MHz}$ . This confirms Option A.

Q8GATE 2015NAT

Consider a four bit D to A converter. The analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in Volts) corresponding to the digital signal 1111 is ________.

🚀 Solve in Practice Mode

📖 Explanation

Step size $=0.0625 \mathrm{V}$ Decimal equivalent $=15$ Analog output $=15 \times 0.0625=0.9375 Volts$

Q9GATE 2011MCQ

The output of a 3-stage Johnson (twisted ring) counter is fed to a digital-to analog (D/A) converter as shown in the figure below. Assume all the states of the counter to be unset initially. The waveform which represents the D/A converter output $v_{o}$ is

🚀 Solve in Practice Mode

📖 Explanation

Sequence of Johnson counter is

\begin{array}{ccccccc} Q_{2} & Q_{1} & Q_{0} & D_{2} & D_{1} & D_{0} & V_{0} \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 & 0 & 4 \\ 1 & 1 & 0 & 1 & 1 & 0 & 6 \\ 1 & 1 & 1 & 1 & 1 & 1 & 7 \\ 0 & 1 & 1 & 0 & 1 & 1 & 3 \\ 0 & 0 & 1 & 0 & 0 & 1 & 1 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 \end{array}

Q10GATE 2008MCQ

In the following circuit, the comparator output is logic "1" if $V_{1} \gt V_{2}$ and is logic "0" otherwise. The D/A conversion is done as per the relations $V_{DAC}=\sum_{n=0}^{3}2^{n-1}b_{n}$ Volts, where $b_{3}$ (MSB), $b_{2}$ , $b_{1}$ , $b_{0}$ (LSB) are the counter outputs. The counter starts from the clear state. The magnitude of the error between $V_{DAC}$ and $V_{\in}$ at steady state in volts is

🚀 Solve in Practice Mode

📖 Explanation

Magnitude of the error between $V_{\mathrm{DAC}}$ and $V_{\text {\in }}$ at steady state $=6.5-6.2=0.3 \mathrm{V}$

Q11GATE 2007MCQ

In the Digital-to-Analog converter circuit shown in the figure below, $V_{R}=10 V$ and R = 10K $\Omega$ The voltage $V_{o}$ is

🚀 Solve in Practice Mode

📖 Explanation

Net current in inverting terminal of op-amp

\begin{aligned} &=\frac{I}{4}+\frac{I}{16}=\frac{5 I}{16} \\ V_{0} &=-R \times \frac{5 I}{16} \\ =&-\frac{10 \times 10^{3} \times 5 \times 1 \times 10^{-3}}{16}=-3.125 \mathrm{V} \end{aligned}

Q12GATE 2006MCQ

A 4-bit D/A converter is connected to a free -running 3-bit UP counter, as shown in the following figure. Which of the following waveforms will be observed at $v_{0}$ ?

🚀 Solve in Practice Mode

📖 Explanation

\begin{array}{ccccccccc} \text { CP } & \rightarrow & 1 & 2 & 3 & 4 & 5 & 6 & 7 \\ & &\downarrow & \downarrow & \downarrow & \downarrow & \downarrow & \downarrow & \downarrow \\ \text { Counter } &\rightarrow & 001 & 010 & 011 & 100 & 101 & 110 & 1000 \\ & & \downarrow & \dagger & \dagger & \downarrow & \downarrow & \downarrow & \downarrow \\ \text { Decoder } & \rightarrow & 0001 & 0010 & 0011 & 1000 & 1001 & 1010 & 0000 \\ & & 1 & 2 & 3 & 8 & 9 & 10 & 0 \end{array}

$D_{2}$ is connected to ground and $Q_{2}$ to $D_{3}$

Q13GATE 2004MCQ

A digital system is required to amplify a binary-encoded audio signal. The user should be able to control the gain of the amplifier from minimum to a maximum in 100 increments. The minimum number of bits required to encode, in straight binary, is

🚀 Solve in Practice Mode

📖 Explanation

\begin{aligned} 2^{n}&\geq100\\ \therefore \quad n&\geq7 \end{aligned}

Q14GATE 2003MCQ

The minimum number of comparators required to build an 8-bits flash ADC is

🚀 Solve in Practice Mode

📖 Explanation

$2^{n}-1=2^{8}-1=255$

Q15GATE 2003MCQ

The circuit shown in the figure is a 4 bit DAC The input bits 0 and 1 are represented by 0 and 5 V respectively. The OP AMP is ideal, but all the resistance and the 5 v inputs have a tolerance of $\pm$ 10%. The specification (rounded to nearest multiple of 5%) for the tolerance of the DAC is

🚀 Solve in Practice Mode

📖 Explanation

\begin{aligned} V_{0} &=-V_{R} \cdot\left[d_{3} \cdot \frac{R}{R}+d_{2} \frac{R}{2 R}+d_{1} \frac{R}{4 R}+d_{0} \frac{R}{8R}\right]\\ \Rightarrow V_{0} &=-V_{R} \cdot \frac{R}{R}[\text { constant }] \end{aligned}

worst case tolerance in $V_{0}=\frac{1.1 \times 1.1}{0.9}=35 \%$

Q16GATE 2002MCQ

The number of comparators required in a 3-bit comparator type ADC is

🚀 Solve in Practice Mode

📖 Explanation

$2^{n}-1=2^{3}-1=7$

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