Interrupt – GATE CSE Computer Organization ArchitecturePractice Questions & PYQs

In a vectored interrupt mechanism, the interrupting device provides the vector address directly to the CPU, allowing immediate branch to the Interrupt Service Routine (ISR). In contrast, a non-vectored interrupt requires the CPU to execute a software routine to poll or check the status registers of various devices to identify the source, which inherently increases latency. Thus, $\text{S1}$ is true.

The daisy-chain interrupt mechanism is a hardware-based approach where an interrupt acknowledge signal propagates serially through the connected devices until it reaches the requesting device. Since this mechanism determines the source of the interrupt via hardware prioritization rather than the CPU performing software polling of each device individually, $\text{S2}$ is false.

When an interrupt occurs in a non-pipelined processor, the CPU must complete its current instruction before responding. After finishing the instruction, the processor saves the current program counter (PC) value to memory, allowing it to resume execution from that point later. Finally, the PC is loaded with the starting address of the Interrupt Service Routine (ISR) to begin handling the interrupt.

The correct sequence of steps is:

1. (iii) The processor finishes the present instruction.
2. (i) The processor saves the content of the program counter.
3. (ii) The program counter is loaded with the start address of the ISR.

For polling: The system polls every 10 ms, and each poll consumes 100 $\mu s$. In 1 second (1000 ms), there are $1000 \text{ ms} / 10 \text{ ms} = 100$ polls.
Total time spent polling in 1 second is $100 \text{ polls} \times 100 \mu s/\text{poll} = 10000 \mu s$.
If a keystroke occurs (1 per second), an additional 200 $\mu s$ is spent processing it. So, total time for polling and processing in 1 second is $10000 \mu s + 200 \mu s = 10200 \mu s$.
$T_1 = 10200 \mu s / 1 \text{ sec} = 10200 \mu s / 10^6 \mu s = 0.0102$.
For interrupts: An interrupt is raised for every keystroke (1 per second), and servicing an interrupt takes 1 ms.
$T_2 = 1 \text{ ms} / 1 \text{ sec} = 1 \text{ ms} / 1000 \text{ ms} = 0.001$.
The ratio $\frac{T_1}{T_2} = \frac{0.0102}{0.001} = 10.2$.

Here's a step-by-step explanation for the given question:

1. Statement I: Daisy chaining is used to assign priorities in attending interrupts. This statement is TRUE. Daisy chaining is a hardware-based method where devices are connected in a chain, and the device closest to the CPU has the highest priority.

2. Statement II: When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. This statement is FALSE. In a vectored interrupt system, the interrupting device directly provides a vector (address or ID) to the CPU, eliminating the need for polling to identify the source. Polling is typically used in non-vectored interrupt scenarios.

3. Statement III: In polling, the CPU periodically checks the status bits to know if any device needs its attention. This statement is TRUE. Polling is a software-based method where the CPU repeatedly checks the status registers of I/O devices to see if any require service.

4. Statement IV: During DMA, both the CPU and DMA controller can be bus masters at the same time. This statement is FALSE. During DMA, the DMA controller temporarily takes over the bus from the CPU to perform data transfers directly between I/O devices and memory, thus only one can be the bus master at a time to avoid conflicts.

Based on the analysis, statements I and III are TRUE.

When an interrupt is issued, the processor follows a specific sequence to handle it and then resume the original task. Let's break down the process:

1. (Q) The processor finishes the execution of the current instruction. The CPU checks for interrupts only after completing the current instruction. It cannot suspend an instruction midway.

2. (P) The processor pushes the process status of L onto the control stack. Before servicing the interrupt, the processor must save the current state of process L (including the Program Counter and other registers) so that it can be resumed later without losing its context. This state is saved on the stack.

3. (T) The processor loads the new PC value based on the interrupt. The processor determines the type of interrupt and uses the interrupt vector table to find the starting address of the corresponding Interrupt Service Routine (ISR). This address is loaded into the Program Counter (PC).

4. (R) The processor executes the interrupt service routine. With the PC now pointing to the ISR, the processor begins executing the ISR's code to handle the specific event that caused the interrupt.

5. (S) The processor pops the process status of L from the control stack. After the ISR completes its task, the saved state of process L is restored by popping it from the stack back into the processor's registers. The PC is restored to the address of the next instruction in process L.

This sequence ensures that the interrupt is handled correctly and the interrupted process can resume exactly where it left off. The correct order is Q, P, T, R, S.

The 8085 microprocessor features five hardware interrupts: $TRAP$, $RST\ 7.5$, $RST\ 6.5$, $RST\ 5.5$, and $INTR$. Interrupts $RST\ 7.5$, $RST\ 6.5$, and $RST\ 5.5$ are classified as maskable, meaning they can be enabled or disabled via software instructions like $SIM$. In contrast, $TRAP$ is the highest priority interrupt and is hardwired to be non-maskable, signifying that it cannot be disabled or masked by any software command. Thus, $TRAP$ is the only unmaskable interrupt in the 8085 architecture.

In the 8085 microprocessor, the TRAP interrupt is internally classified as RST 4.5. The vector address for any hardware interrupt is calculated by multiplying its associated RST number by 8. Applying this rule:
$Vector Address = 4.5 \times 8 = 36 \text{ (decimal)}$
To find the memory location, we convert the decimal value $36$ into its hexadecimal equivalent:
$36_{10} = (2 \times 16^1) + (4 \times 16^0) = 24_{16}$
Thus, the vector address (ISR location) for the TRAP interrupt is $24H$.

Interrupts are prioritized based on their urgency and potential impact on system stability. A CPU temperature sensor interrupt indicates a critical hardware condition that could lead to system failure if not addressed immediately. It is generally given the highest priority to prevent damage. Other interrupts like mouse, keyboard, or hard disk completion are less critical and can be deferred.

A CPU prioritizes the completion of the current instruction to maintain data consistency and program state. Interrupts are typically checked only after the current instruction has fully executed. This prevents an instruction from being partially completed and then interrupted, which could lead to an unpredictable system state. Therefore, the CPU checks for pending interrupts in the interrupt register at the end of the current instruction's execution cycle.

In synchronous I/O, the calling process blocks while the I/O controller performs the operation, and an ISR is required to wake the process upon completion, making statements C and D true. The question assumes a classification where ISRs are exclusively associated with synchronous I/O, rendering statement A true in this specific context. Because statement A asserts that ISRs are not used for asynchronous I/O, statement B, which claims they are used in both, must be the incorrect assertion. Consequently, statement B is the one that is not true.

The minimum time for $I_3$ to execute occurs when no other interrupts are pending, consisting only of its response time and execution time: $4.5\,\mu\text{s} + 20\,\mu\text{s} = 24.5\,\mu\text{s}$.

The maximum time occurs when $I_3$ arrives simultaneously with higher-priority interrupts $I_1$ and $I_2$. Because each interrupt requires a response time of $4.5\,\mu\text{s}$ before execution, $I_3$ must wait for both $I_1$ and $I_2$ to complete their response and execution phases.

The total maximum time is calculated as the sum of the response and execution times for all three interrupts:
$(25\,\mu\text{s} + 4.5\,\mu\text{s}) + (35\,\mu\text{s} + 4.5\,\mu\text{s}) + (20\,\mu\text{s} + 4.5\,\mu\text{s})$
$= 29.5\,\mu\text{s} + 39.5\,\mu\text{s} + 24.5\,\mu\text{s} = 93.5\,\mu\text{s}$

Thus, the possible range for $I_3$ to be executed is $24.5\,\mu\text{s}$ to $93.5\,\mu\text{s}$.

When an I/O interrupt signal is asserted, the CPU does not immediately cease execution to maintain system stability and state integrity. To ensure instruction atomicity, the CPU must complete the execution of the current instruction cycle. Upon completion of this cycle, the CPU checks for any pending interrupt requests. If a request is detected, it saves the current Program Counter ($PC$) and processor status word onto the stack. Finally, the CPU branches to the memory address of the specific Interrupt Service Routine ($ISR$) to handle the I/O request.

The Intel 8085 TRAP interrupt is a non-maskable, high-priority request requiring a transition from $0 \rightarrow 1$ to initiate the interrupt sequence. This positive edge ($+ve$ edge) is essential to set the internal status latch and register the request. The signal must then be held high to ensure the processor completes the acknowledgment cycle. Subsequently, the interrupt request is cleared when the signal returns to a low state ($1 \rightarrow 0$), which functions as a negative edge ($-ve$ edge) to reset the status flip-flop. Consequently, the hardware logic is designed to monitor both the positive edge for activation and the negative edge for deactivation, characterizing it as triggered by both.

Interrupts are mechanisms used by devices to signal the CPU for attention, classified by how the Interrupt Service Routine (ISR) address is determined. In a non-vectored interrupt, the CPU is not informed of the source and must execute polling or jump to a fixed memory location to identify the device. Conversely, a vectored interrupt requires the interrupting device to directly transmit a specific code or memory address, called the interrupt vector, to the CPU. This vector provides the starting memory address of the corresponding ISR, allowing the CPU to immediately identify the source and execute the required handler. Since the question specifies that the external device supplies its specific address along with the request, it directly satisfies the definition of a vectored interrupt.

Multiple devices can share a single $Interrupt Request$ line by logically OR-ing their outputs, ensuring the CPU is alerted if any device triggers an interrupt. To support vectoring and source identification, the system uses the single $Interrupt Grant$ line in a daisy-chain configuration. When the CPU issues a grant, the signal propagates serially through the devices; the first requesting device intercepts the grant and places its specific address (vector) onto the data bus. Because the requesting device can provide its unique interrupt vector during this acknowledge cycle, both multiple interrupting devices and vectored interrupts are fully supported with only these two lines.

When an interrupt request is received via the $INTR$ line, the microprocessor completes the current instruction and, if interrupts are enabled, acknowledges the request by asserting the $\overline{INTA}$ (Interrupt Acknowledge) signal (active low). This $\overline{INTA}$ signal acts as a trigger for the external device, signaling it to place the necessary interrupt instruction opcode (such as $RST$ or part of a $CALL$ sequence) onto the data bus. The microprocessor then reads this byte from the data bus during the specific $\overline{INTA}$ machine cycle to identify the interrupt service routine. Therefore, the device places the instruction on the bus exclusively when the $\overline{INTA}$ signal is active.

Software interrupts, often termed traps or system calls, are mechanisms designed to switch a processor's privilege level from User Mode to Kernel Mode. Because User Mode applications are restricted from executing sensitive privileged instructions-such as direct hardware I/O or memory management-they cannot perform these tasks themselves. When an application requires such a system service, it triggers a software interrupt to intentionally transfer control to the Operating System kernel. The kernel, running with higher privileges, performs the requested operations on behalf of the user process. This controlled transition is the standard way to securely bridge the gap between restricted user applications and the privileged operations managed by the kernel.

A CPU switch from privileged to non-privileged mode indicates the operating system is returning control to a user application. Unlike the transition from user to kernel mode, which requires a hardware or software interrupt, the reverse transition does not require any interrupt. The kernel performs this by updating the processor status register to set the mode bit from $1$ (privileged) to $0$ (non-privileged). In this specific architecture, the instruction used to modify the mode bit is classified as a non-privileged instruction. Consequently, the transition is achieved using a non-privileged instruction that does not trigger an interrupt.

The 8085 microprocessor processes interrupts by sampling input pins to ensure logical consistency and preserve the system state. To maintain architectural integrity, the CPU cannot abort an instruction mid-cycle; it must complete the entire instruction execution. The $TRAP$ pin is sampled by the control unit during the final $T$-state of the last machine cycle of the currently executing instruction. This design ensures that the processor finishes the fetch, decode, and execute sequence before transitioning to the interrupt service routine. Consequently, the processor verifies the $TRAP$ signal status specifically at the boundary marking the conclusion of every instruction execution.

Interrupt priority is primarily assigned based on the data transfer rate ($v$) of the I/O device to maximize system efficiency.
Devices with higher data transfer rates require more frequent and immediate servicing to prevent buffer overflows and data loss.
Among the options, the hard disk has the highest throughput capacity, typically measured in $GB/s$ or $MB/s$, which is significantly faster than the mechanical speeds of the other devices.
Quantitatively, we observe the relationship $v_{Hard Disk} \gg v_{Floppy Disk} > v_{Printer} > v_{Keyboard}$.
Therefore, the hard disk receives the highest interrupt priority to ensure data integrity and prevent system bottlenecks.