Interrupt Practice Questions

When an interrupt occurs in a non-pipelined processor, the CPU must complete its current instruction before responding. After finishing the instruction, the processor saves the current program counter (PC) value to memory, allowing it to resume execution from that point later. Finally, the PC is loaded with the starting address of the Interrupt Service Routine (ISR) to begin handling the interrupt.

The correct sequence of steps is:

1. (iii) The processor finishes the present instruction.
2. (i) The processor saves the content of the program counter.
3. (ii) The program counter is loaded with the start address of the ISR.

For polling: The system polls every 10 ms, and each poll consumes 100 $\mu s$. In 1 second (1000 ms), there are $1000 \text{ ms} / 10 \text{ ms} = 100$ polls.
Total time spent polling in 1 second is $100 \text{ polls} \times 100 \mu s/\text{poll} = 10000 \mu s$.
If a keystroke occurs (1 per second), an additional 200 $\mu s$ is spent processing it. So, total time for polling and processing in 1 second is $10000 \mu s + 200 \mu s = 10200 \mu s$.
$T_1 = 10200 \mu s / 1 \text{ sec} = 10200 \mu s / 10^6 \mu s = 0.0102$.
For interrupts: An interrupt is raised for every keystroke (1 per second), and servicing an interrupt takes 1 ms.
$T_2 = 1 \text{ ms} / 1 \text{ sec} = 1 \text{ ms} / 1000 \text{ ms} = 0.001$.
The ratio $\frac{T_1}{T_2} = \frac{0.0102}{0.001} = 10.2$.

Here's a step-by-step explanation for the given question:

1. Statement I: Daisy chaining is used to assign priorities in attending interrupts. This statement is TRUE. Daisy chaining is a hardware-based method where devices are connected in a chain, and the device closest to the CPU has the highest priority.

2. Statement II: When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. This statement is FALSE. In a vectored interrupt system, the interrupting device directly provides a vector (address or ID) to the CPU, eliminating the need for polling to identify the source. Polling is typically used in non-vectored interrupt scenarios.

3. Statement III: In polling, the CPU periodically checks the status bits to know if any device needs its attention. This statement is TRUE. Polling is a software-based method where the CPU repeatedly checks the status registers of I/O devices to see if any require service.

4. Statement IV: During DMA, both the CPU and DMA controller can be bus masters at the same time. This statement is FALSE. During DMA, the DMA controller temporarily takes over the bus from the CPU to perform data transfers directly between I/O devices and memory, thus only one can be the bus master at a time to avoid conflicts.

Based on the analysis, statements I and III are TRUE.

When an interrupt is issued, the processor follows a specific sequence to handle it and then resume the original task. Let's break down the process:

1. (Q) The processor finishes the execution of the current instruction. The CPU checks for interrupts only after completing the current instruction. It cannot suspend an instruction midway.

2. (P) The processor pushes the process status of L onto the control stack. Before servicing the interrupt, the processor must save the current state of process L (including the Program Counter and other registers) so that it can be resumed later without losing its context. This state is saved on the stack.

3. (T) The processor loads the new PC value based on the interrupt. The processor determines the type of interrupt and uses the interrupt vector table to find the starting address of the corresponding Interrupt Service Routine (ISR). This address is loaded into the Program Counter (PC).

4. (R) The processor executes the interrupt service routine. With the PC now pointing to the ISR, the processor begins executing the ISR's code to handle the specific event that caused the interrupt.

5. (S) The processor pops the process status of L from the control stack. After the ISR completes its task, the saved state of process L is restored by popping it from the stack back into the processor's registers. The PC is restored to the address of the next instruction in process L.

This sequence ensures that the interrupt is handled correctly and the interrupted process can resume exactly where it left off. The correct order is Q, P, T, R, S.

Interrupts are prioritized based on their urgency and potential impact on system stability. A CPU temperature sensor interrupt indicates a critical hardware condition that could lead to system failure if not addressed immediately. It is generally given the highest priority to prevent damage. Other interrupts like mouse, keyboard, or hard disk completion are less critical and can be deferred.

A CPU prioritizes the completion of the current instruction to maintain data consistency and program state. Interrupts are typically checked only after the current instruction has fully executed. This prevents an instruction from being partially completed and then interrupted, which could lead to an unpredictable system state. Therefore, the CPU checks for pending interrupts in the interrupt register at the end of the current instruction's execution cycle.