Interrupt – GATE CSE Computer Organization ArchitecturePractice Questions & PYQs

Most processors utilize an interrupt enable flag, such as the $I$ bit in the Status Register, to regulate incoming requests. Unless this hardware flag is explicitly set, the CPU logic masks maskable interrupts, ensuring they remain pending and are not serviced by the processor. This mechanism is essential for defining critical sections of code where atomicity is required. Conversely, Option B is incorrect because CPUs can often handle interrupts mid-loop or between iterations, and Option D is false as modern processors support both edge and level-triggered interrupt signals. Therefore, the explicit hardware requirement to enable interrupts serves as a functional prerequisite for interrupt processing.

The vector address for 8085 hardware interrupts RST $n$ is calculated using the formula $8 \times n$ (in decimal). For the RST 7.5 interrupt, we substitute $n = 7.5$ into the equation:
$\text{Address} = 8 \times 7.5 = 60_{10}$
To determine the corresponding hexadecimal address, we convert the decimal value $60$ to base-16.
Since $60 = 3 \times 16 + 12$, where the remainder $12$ is represented by $C$ in hexadecimal, the result is $3C_{16}$.
Padding this with leading zeros to match the memory addressing scheme, we arrive at the location $003CH$.

Interrupt handling mechanisms are categorized into non-vectored and vectored systems. In non-vectored interrupts, the CPU jumps to a fixed memory address, requiring software polling to identify the interrupting device. In contrast, a vectored interrupt relies on hardware support where the interrupting source transmits a unique identifier, called an interrupt vector, directly to the processor. The processor then uses this vector as an index into an Interrupt Vector Table to retrieve the specific branch address for the required service routine. Since the device explicitly supplies this routing information, option B accurately defines the operation of a vectored interrupt.

The central NOR gate produces $z = \overline{x + y}$.
The top gate output is $A = \overline{x + z} = \overline{x + \overline{x+y}} = \overline{x} \cdot (x + y) = \overline{x}y$.
The bottom gate output is $B = \overline{y + z} = \overline{y + \overline{x+y}} = \overline{y} \cdot (x + y) = x\overline{y}$.
The final NOR gate computes $f(x, y) = \overline{A + B} = \overline{\overline{x}y + x\overline{y}}$.
Since $\overline{x}y + x\overline{y}$ is the XOR function $x \oplus y$, the output is $f(x, y) = \overline{x \oplus y}$, which represents the exclusive NOR logic.

The 8085 TRAP interrupt is a non-maskable, vectorable interrupt that automatically forces the program counter to memory location $0024H$. Option A is incorrect because TRAP is a hardware-initiated interrupt sequence, not the execution of a standard RST instruction. Option B is incorrect as it describes the INTR mechanism, where an external device provides an opcode via the data bus. Option C is incorrect because the TRAP vector address is $0024H$, not $20H$ (which corresponds to RST 4). Option D is clearly false, making E the correct choice.

An interrupt is an asynchronous signal requesting immediate CPU attention for a task, such as I/O handling. Because CPU instructions are atomic operations, interrupting the process mid-instruction would corrupt the internal processor state, including registers, flags, and the Program Counter ($PC$). Therefore, CPU architecture requires the completion of the current fetch-decode-execute cycle to ensure the instruction's side effects are fully committed. Once the instruction finishes, the processor saves the current context to the stack and updates the $PC$ with the address of the Interrupt Service Routine (ISR). This specific sequence guarantees that the transition to the ISR occurs safely, maintaining system stability.