Semiconductor Electronics – JEE Main PhysicsPractice Questions & PYQs

Digital logic circuits produce a high output-represented as a binary 1-only when the specific Boolean conditions defined by the internal gate configuration are satisfied. Evaluating the input sets reveals that the combination 1101 aligns with the required logic states, such as enabling specific AND or OR paths, to allow current flow to the LED where the variables $A=1$, $B=1$, $C=0$, and $D=1$. This specific configuration is the only input set that fulfills the functional requirements of the underlying logic diagram to generate a high signal.

The Boolean expression $Y = A \cdot \bar{B}$ defines a logic gate where the output $Y$ is high only when input $A$ is 1 and input $B$ is 0. By calculating the output for all possible combinations of inputs $(A, B)$, the resulting sequence of $Y$ values is $0, 0, 1, 0$ for inputs $(0,0), (0,1), (1,0),$ and $(1,1)$ respectively, which corresponds to the truth table provided in the first option.

The time constant of an RC circuit represents the rate at which the capacitor charges or discharges, determined by the product of the equivalent resistance and the capacitance as defined by the formula $\tau = R_{\text{eq}}C$. In this circuit, the resistance encountered by the current is the sum of the fixed resistor and the internal resistance of the forward-biased diodes, leading to an equivalent resistance of 100 Ω + 10 Ω = 110 Ω.

With the capacitance given as 20 μF, or 20 × 10⁻⁶ F, we calculate the time constant by multiplying the total resistance and the capacitance, resulting in $\tau = 110 \times 20 \times 10^{-6}\,\text{s}$. Carrying out this multiplication yields 2200 × 10⁻⁶ s, which simplifies to 2.2 × 10⁻³ s. By matching this result to the required form $\alpha \times 10^{-3}\,\text{s}$, the value of α is identified as 2.2.

The voltage regulator circuit maintains a constant output voltage by dropping the excess input voltage across the series resistor $R_s$. The voltage across this series resistor is given by the difference between the supply voltage and the Zener voltage, $V_{R_s} = V_{\in} - V_z = 25\ \text{V} - 5\ \text{V} = 20\ \text{V}$.

The total current $I_s$ flowing through the series resistor must satisfy the regulation requirements for both the load and the Zener diode. Based on the requirement that the total current is four times the load current of $I_L = 5\ \text{mA}$, the total current is $I_s = 4 \times 5\ \text{mA} = 20\ \text{mA} = 0.02\ \text{A}$. Applying Ohm's Law, the resistor value is $R_s = \frac{V_{R_s}}{I_s} = \frac{20\ \text{V}}{0.02\ \text{A}} = 1000\ \Omega$.

To protect a Zener diode from overheating, the circuit current must be limited such that the power dissipation does not exceed 0.5 W. Given the Zener voltage of 10 V, the maximum current the device can safely handle is calculated as $I = \frac{0.5}{10} = 0.05$ A.

Since the diode is connected to a 25 V supply and maintains a constant 10 V in breakdown, the series resistor must drop the excess voltage, which is $25 - 10 = 15$ V. By applying Ohm's law to this voltage drop using the maximum allowable current, the minimum safe resistance required for the circuit is $R = \frac{15}{0.05} = 300$ $\Omega$.

When a diode operates under reverse bias, the depletion region expands to obstruct the path of majority charge carriers, resulting in a minimal, stable leakage current. This current stays largely constant across varying voltages until it hits a critical breakdown threshold where the current climbs rapidly, confirming the validity of the assertion. The reason given is incorrect because the movement of charges in a reverse-biased state is governed by the drift of minority charge carriers, not majority charge carriers as stated.

Clipping circuits utilize the reverse breakdown characteristic of Zener diodes to maintain a stable $v_o(t)$ regardless of fluctuations in $v_{\in}(t)$. During the positive cycle, the middle branch's diode acts as a forward-biased path, allowing the Zener diode to clamp the voltage at 5 V while the segment between X and Y functions as an open circuit. Conversely, as the input transitions to the negative half cycle, the central branch becomes inactive, causing the components situated between X and Y to engage in Zener breakdown and fix the output at -5 V.

Limiting the power dissipation is critical to preventing damage to the LED, a condition governed by the relationship $P = VI$. Given the maximum power of 2 mW and a current of 0.5 mA, the voltage drop across the LED is determined by $V_{\text{LED}} = \frac{P}{I}$, which equates to 4 V.

By Kirchhoff's voltage law, the input supply of 5 V is distributed between the resistor and the LED, so the voltage drop across the series resistor is 5 V minus 4 V, or 1 V. Applying Ohm's law in the form
$R_S = \frac{V_{R_S}}{I}$
with the voltage of 1 V and current of 0.5 mA, we find the minimum resistance required is 2 kΩ.

A NAND gate functions as an inverted AND operation, producing a low output only when all inputs are high. The logical behavior is defined by the Boolean expression $Y = \overline{A \cdot B}$, which dictates that the output $Y$ is logic $0$ solely when both inputs $A$ and $B$ are logic $1$, and logic $1$ in all other input combinations.

The output $Y$ of a logic circuit is uniquely determined by the Boolean function characterizing the gate configuration, where the truth table systematically maps every specific combination of input states ($A, B, C, D$) to its corresponding output $Y$. The values of $Y$ in the correct truth table are obtained by evaluating the circuit's Boolean expression for each set of inputs, ensuring the binary output level consistently reflects the logical operation performed on the input variables. This tabular representation in the selected option accurately records these output states for all given input combinations, thereby satisfying the functional requirements of the logic gate.

The protective resistance $R_s$ in a Zener voltage regulator is determined by Ohm's Law using the relation $R_s = \frac{V_i - V_z}{I_{z_{max}}}$, where $V_i$ is the source voltage, $V_z$ is the breakdown voltage, and $I_{z_{max}}$ is the maximum allowable Zener current. The maximum current is calculated from the power dissipation rating $P_z$ as $I_{z_{max}} = \frac{P_z}{V_z} = \frac{0.4}{10} = 0.04 \text{ A}$ The voltage drop across the protective resistor is found by calculating the difference between the source voltage and the Zener voltage, giving $V_R = 15 - 10 = 5 \text{ V}$. Substituting these values into the resistance formula results \in $R_s = \frac{5}{0.04} = 125 \text{ } \Omega$

According to Kirchhoff's Voltage Law, the sum of the voltages in a closed loop is zero, which for the forward-biased diode loop is expressed as $V_{source} - I \cdot R - V_D = 0$. Rearranging this equation to solve for the diode current yields $I = \frac{V_{source} - V_D}{R}$. Substituting the circuit parameters of a $19.5 \text{ V}$ source and a $1 \text{ k}\Omega$ equivalent resistance along with the forward voltage drop of $0.7 \text{ V}$ results in $I = \frac{19.5 - 0.7}{1000} = 18.8 \text{ mA}$.

The fundamental principle governing this circuit is the distributive property of Boolean algebra, which allows us to factor out the common term B from the expression $A \cdot B + \overline{A} \cdot B$. By factoring B, we reach the form $(A + \overline{A}) \cdot B$. Since the sum of any variable and its complement is always unity, this expression simplifies directly to $1 \cdot B$, confirming that the output Y is simply equal to B.

In a DC steady-state circuit, a capacitor acts as an open circuit, meaning no current flows through the branch containing it, and the potential difference across its terminals is determined by the external resistive network. The charge $Q$ stored on the capacitor is calculated using the formula $Q = CV$, where $C$ is the capacitance and $V$ is the potential difference across the capacitor. By applying the voltage divider rule to the resistive network in the circuit, the potential difference is determined to be $5\,V$, and with the capacitance value of $2\,\mu F$, the final charge is calculated as $Q = 2\,\mu F \times 5\,V = 10\,\mu C$.

Boolean algebra laws allow us to distill complex logic gate combinations into a manageable expression. Starting with the expression $Y = \overline{\overline{A} + B + \overline{A} B}$, observe that the component $\overline{A} + \overline{A} B$ simplifies directly to $\overline{A}$ because the presence of $\overline{A}$ inherently satisfies the condition regardless of the value of $B$. This reduction transforms the overall expression into $\overline{\overline{A} + B}$, which further simplifies by De Morgan's Law into $\overline{\overline{A}} \cdot \overline{B}$, ultimately leaving us with the simplified gate equivalent $Y = A \overline{B}$.

Using this simplified logic, we test the required inputs to determine the outputs. For the case where $A = 1$ and $B = 1$, the expression becomes $1 \cdot \overline{1}$, or $1 \cdot 0$, which yields an output of $0$. Applying the same logic to the case where $A = 0$ and $B = 1$, we get $0 \cdot \overline{1}$, or $0 \cdot 0$, resulting in an output of $0$ once again.

A NAND gate produces a low output only when both input signals are high, yielding a high output for the input combinations $(0,0)$, $(0,1)$, and $(1,0)$, and a low output for the combination $(1,1)$. This logical operation is defined by the Boolean expression $z = \overline{n \cdot m}$, where the output is the complement of the AND operation of inputs $n$ and $m$. These specific input-output pairs match the truth table provided in the first option.

In a p-n junction diode, the formation of the depletion region is governed by the principle of charge neutrality, which dictates that the total number of uncovered acceptor ions on the p-side must equal the total number of uncovered donor ions on the n-side. This relationship is expressed as $N_A x_p = N_D x_n$, where $N_A$ and $N_D$ represent the doping concentrations and $x_p$ and $x_n$ are the widths of the depletion layer on the respective sides. Since the p-side has a significantly lower doping concentration of $10^{15}$ atoms/cm^3 compared to the n-side concentration of $10^{18}$ atoms/cm^3, the depletion region must extend further into the p-side to accumulate enough uncompensated charges to maintain equilibrium, resulting in a larger width on that side.

For both LEDs to function, the circuit inputs must satisfy the activation criteria for both components simultaneously. The second indicator requires that both $A = 1$ and $C = 1$ are held, while the first indicator activates whenever the input pair $(A, B)$ is set to $(0, 1)$, $(1, 0)$, or $(1, 1)$. By requiring $A = 1$ and $C = 1$ for the second LED, we identify that the input set $A = 1, B = 0, C = 1$ fulfills the necessary logic, as this combination satisfies the requirement for the second light and matches the $(1, 0)$ condition required to illuminate the first.

A diode AND gate configuration functions by clamping the output voltage to the lowest potential present at its inputs through a conducting diode, which occurs whenever at least one input is at a logic low state. When both inputs $A$ and $B$ are held at a logic high, both diodes are reverse-biased, effectively disconnecting the inputs from the output and allowing the pull-up resistor to bring the output $C$ to the logic high state. This operation satisfies the logical AND relationship $C = A \cdot B$, as the output is high only if both inputs are concurrently at a logic high level.

The Boolean expression $C = \overline{x+y}$ defines the behavior of a logic circuit where the inputs $x$ and $y$ are combined using an OR operation and then inverted. Since an OR gate performs the addition $x+y$ and the bar indicates a NOT operation, the sequential combination of these functions is the fundamental definition of a NOR gate. This configuration produces an output that is high only when both inputs are low, confirming that the circuit functions as a NOR gate.