Semiconductor Electronics – JEE Main PhysicsPractice Questions & PYQs

The logic circuit implements the Boolean operation defined by the expression $Y = A + \overline{B}$. Given the input $B = 1010$, the bitwise complement is calculated as $\overline{B} = 0101$. Performing a bitwise OR operation between $A = 1101$ and this complement yields the result $Y = 1101 + 0101 = 1101$.

Photovoltaic and optoelectronic devices operate according to distinct principles regarding junction geometry and biasing requirements. Solar cells are designed with a wide junction area to efficiently harvest light energy and do not require any external bias to function, which confirms that statement B is correct while invalidating statement A. Similarly, while LEDs rely on forward bias to emit light as described in statement E, their light intensity does not increase continuously with current; instead, it saturates once a certain current level is exceeded, proving that statement D is incorrect.

The provided truth table reveals that the output $Y$ directly follows the state of input $A$, remaining at 0 when $A$ is 0 and at 1 when $A$ is 1, regardless of the value of $B$. Evaluating the Boolean expression for the correct circuit, $(A+B) \cdot A$, allows us to distribute the terms to get $A \cdot A + A \cdot B$, which simplifies to $A + A \cdot B$. Applying the identity $A \cdot A = A$ and the absorption law reduces this entire expression to $A$, confirming that this specific gate configuration accurately replicates the behavior shown in the table.

Zener diodes function as voltage regulators by maintaining a stable potential difference equal to their breakdown rating when operating in the reverse breakdown region. Since the Zener diode is connected in parallel with the $400\,\Omega$ resistor, it forces the voltage across that resistor to remain constant at $4\,\text{V}$. Applying Ohm's law, $I = \frac{V}{R}$, the current flowing through this branch is calculated as $I = \frac{4}{400}$, which yields $0.01\,\text{A}$, or $10\,\text{mA}$.

Applying De Morgan's laws simplifies the logic expressions for both circuit outputs. For $P$, the expression $\overline{AB}(\overline{A}+\overline{B})$ reduces to $\overline{AB} \cdot \overline{AB}$, which evaluates to $0$ under the given input conditions. The expression for $Q$, defined as $\overline{(\overline{A}+\overline{B})+AB}$, simplifies because $(\overline{A}+\overline{B})$ is equivalent to $\overline{AB}$, making the interior term $\overline{AB} + AB$, which is a tautology equal to $1$. Inverting this interior value leads to $Q$ being $0$.

Boolean algebra simplifies the circuit logic expressed as $C = (A + B) \cdot A$ through the distributive law, yielding $C = A \cdot A + A \cdot B$. Because $A \cdot A = A$, the equation becomes $C = A + A \cdot B$, which simplifies further to $C = A(1 + B)$ upon factoring out the variable $A$. Since any variable OR-ed with $1$ results in $1$, the final output $C = A$ confirms that the output must mirror the input $A$ regardless of the value of $B$, as demonstrated in the second truth table.

A Zener diode voltage regulator maintains a steady output by dividing the incoming supply current between the diode and the load. Since the total current through the series resistor is the sum of the Zener current and the load current, the condition $I_Z = 4 I_L$ implies that the total series current is $I_S = I_Z + I_L = 5 I_L$. The voltage drop across the series resistor is $25 - 5 = 20 \text{ V}$, which means the total series current is $I_S = \frac{20}{400} = 0.05 \text{ A}$, or $50 \text{ mA}$. Setting $5 I_L = 50 \text{ mA}$ results in $I_L = 10 \text{ mA}$, and applying Ohm's law to the load yields $R_L = \frac{5}{10 \times 10^{-3}} = 500 \Omega$.

An $n$-type semiconductor is formed by doping an intrinsic material with pentavalent atoms, which donate surplus electrons and establish them as majority carriers, leaving holes as minority carriers. Thermal equilibrium governs the concentration of these carriers through the law of mass action, $n_e n_h = n_i^2$, which renders statement (C) false as the product is strictly equal to $n_i^2$. Because minority holes are generated strictly by thermal excitation of electrons from the valence band rather than by the ionization of donor atoms, statement (E) is accurate.

This logic circuit functions as a NAND gate, which follows the Boolean expression $Y = \overline{A \cdot B}$. Since we require the output $Y=0$, the internal product $A \cdot B$ must equal $1$ because the final operation inverts the result. Given that an AND product reaches a high state only when both inputs are active, this specific output condition occurs when $A=1$ and $B=1$.

The Boolean expression $Y = A \overline{B} C + \overline{A} \overline{C}$ can be realized by observing that the second term $\overline{A} \overline{C}$ is logically equivalent to the NOR operation $\overline{A+C}$ according to De Morgan's Law. Configuration A effectively constructs the required sum-of-products by using separate AND gates for both product terms along with the necessary NOT gates for inversion, while configuration B simplifies the implementation by using a NOR gate to represent the $\overline{A} \overline{C}$ term directly. Configuration C is incompatible with the required sum-of-products logic because its reliance on a 3-input OR gate does not align with the product-sum structure of the expression.

Boolean simplification relies on De Morgan's laws and fundamental algebraic identities to reduce complex gate configurations into their simplest functional form. Applying De Morgan's theorem to the expression $Y = \overline{\overline{AB}(\overline{A+B})}$ yields the sum $AB + A + B$ by canceling the double negations. Factoring the terms as $A(B + 1) + B$ allows for the reduction of the expression to $A + B$, confirming that the circuit performs the logic of an OR gate.

The Exclusive-OR (XOR) gate logic is defined by the boolean expression $Y = A \oplus B = A\overline{B} + \overline{A}B$, which dictates that the output is high only when the two inputs differ. Specifically, for input pairs $(0,0)$ and $(1,1)$, the output is $0$ because the logic levels are identical, whereas for input pairs $(0,1)$ and $(1,0)$, the output is $1$ because the inputs are complementary. This results in a truth table column for $Y$ reading $0, 1, 1, 0$ for the ordered input combinations of $(0,0), (0,1), (1,0),$ and $(1,1)$.

The Boolean expression for the provided logic circuit is $Y = \overline{A \overline{B} + AB}$. By factoring out variable $A$, we can apply the fundamental Boolean identity where $\overline{B} + B = 1$, which reduces the entire expression to $\overline{A}$. This simplification demonstrates that the circuit functions exactly like a simple NOT gate that takes $A$ as its sole input.

Ohm's Law provides the necessary framework for determining current and voltage distribution once the total resistance of the circuit is simplified to $R_{\text{eq}} = 6 \Omega$. By applying the relationship $I = \frac{V}{R}$ with the source voltage and total resistance, the current flowing through the ammeter is determined to be $I = 1 A$. The potential difference across individual segments is found using $V = IR$, which shows that the potential across $CD$ is $V_{CD} = 4 V$, whereas the potential drop across $AB$ is $V_{AB} = 2 V$. These calculations confirm that the observations identifying the total circuit resistance, ammeter current, and the potential difference across $CD$ are the correct conclusions.

The logic circuit functions as a NOR gate, represented by the expression $\overline{X+Y}$. Because an OR operation produces a high signal when at least one input is active, the inverted output of this circuit is forced to zero whenever $X=1$ or $Y=1$. Consequently, the output remains low for the combinations $X=0, Y=1$, $X=1, Y=0$, and $X=1, Y=1$, while it stays high for $X=0, Y=0$.

Determining the missing logic gate requires comparing the provided truth table output against the characteristic boolean operations of standard logic gates. Every gate produces output values dictated by specific logical functions, and the truth table must correspond to the behavior of one of these gates. When testing the provided table values against the behavior of NOR, NAND, OR, and AND gates, the resulting output pattern fails to coincide with the expected output of any of these standard logic functions. Because the given binary output sequence does not align with the functional requirements of any of the listed gates, none of the available options represent a valid solution.

A diode enters forward bias when the electric potential applied to its $p$-side is higher than the potential applied to its $n$-side. By examining the voltage connections in each circuit, you can identify those that adhere to this requirement by comparing the relative terminal voltages. Configurations (B), (C), and (E) represent the specific cases where the potential on the $p$-side exceeds that on the $n$-side, successfully fulfilling the condition for forward bias.

An ideal diode behaves as an open switch when reverse biased and as a short circuit when forward biased, which determines the potential at the output node. Since $D_1$ is reverse biased, it acts as an open connection, whereas the forward biased $D_2$ creates a direct path to ground. This configuration clamps the output terminal to the ground potential, resulting in $V_{out} = 0$.

When diodes are oriented in forward bias, they act as ideal conductors, permitting current to flow through the circuit without obstruction. Given that the diodes are actively conducting, the circuit effectively presents a total resistance of 10 ohms to the 5 V source. By applying Ohm's law, the current $I$ through the battery is determined as follows:

$I = \frac{5}{10} = 0.5$ A

When a Zener diode operates in its breakdown region, it acts as a fixed voltage source, maintaining a constant potential difference of 10 V across the parallel load. The load current is calculated using Ohm's law as $I_L = \frac{10}{500}$, which equals 20 mA, while the total current supplied through the series resistor is $I_s = \frac{10}{200}$, resulting in 50 mA. By applying Kirchhoff's current law at the node, the Zener current is determined by the difference between the supply current and the load current, giving $I_Z = 50 - 20 = 30$ mA.