Q21GATE 2015MCQ

A three bit pseudo random number generator is shown. Initially the value of output $Y \equiv Y_{2} Y_{1} Y_{0}$ is set to 111. The value of output Y after three clock cycles is

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Q22GATE 2014MCQ

The circuit shown in the figure is a

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Q23GATE 2014NAT

Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is______

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📖 Explanation

The circuit or the counter given is the asynchronous counter in which the clock is applied to first flip flop only and the remaining flip flop take the clock from the previous flip flops outputs. As we know that 1 flip flop divides the frequency by 2. So, output of $Q_{3}$ is taken at $4^{th}$ flip-flop. So, division of frequency be f/16. $\therefore$ Frequency (in kHz) of the waveform of $Q_{3} =\frac{1 \mathrm{MHz}}{16}=62.5 \mathrm{kHz}$

Q24GATE 2014MCQ

The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is

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📖 Explanation

Initially $Q_{1}=Q_{2}=0$ Truth table of JK: Case-1: $1^{\text {st }}$ clock pulse

\begin{aligned} Q_{1}=&0, \bar{Q}_{1}=1, Q_{2}=0, \bar{Q}_{2}=1 \\ \text{So, }\quad J_{1}&=1, K_{1}=0 and J_{2}=0, K_{2}=1 \\ \text{So }\quad Q_{1}^{\prime}&=1, \quad Q_{2}^{+}=0 \end{aligned}

Case-2:

\begin{aligned} Q_{1} &=1, Q_{2}=0 \\ \bar{Q}_{1} &=0, \quad \bar{Q}_{2}=1 \\ \text{So,} \quad J_{1}&=1, \quad J_{2}=1 \\ K_{1}&=0 \quad K_{2}=0\\ \text { So } \quad Q_{1}^{+}&=1, \quad Q_{2}^{+}=1 \end{aligned}

Case-3:

\begin{aligned} Q_{1}&=1, \quad \bar{Q}_{1}=0, Q_{2}=1, \bar{Q}_{2}=0 \\ J_{1} &=0, K_{1}=1, J_{2}=1, K_{2}=0 \\ Q_{1}^{+} &=0, \quad Q_{2}^{+}=1 \end{aligned}

So, the sequence will be 01100.

Q25GATE 2014MCQ

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4.

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📖 Explanation

So, according to waveform Solution waveform $W_{3}$ satisfies it

Q26GATE 2012MCQ

The state transition diagram for the logic circuit shown is

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📖 Explanation

When A = 1, then Q will be selected by MUX and feedback to flipflop which gives output 0 again. So at A = 1 it holds its state. When A = 0, then $\bar{Q}$ will be selected by MUX and feedback to flipflop and output will be inverted. So for A = 1 it holds the state and for A = O it interchange the state i.e. if Q = 0 then it will go to Q = 1 and if Q = 1 then it will go to Q = 0. So option (D) is correct option.

Q27GATE 2012MCQ

Consider the given circuit. In this circuit, the race around

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Q28GATE 2011MCQ

When the output Y in the circuit below is '1', it implies that data has

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📖 Explanation

Y=1, it is possible only when both flip-flop outputs are '1'. It means before applying clock both flipflop input should be '1'. Before applying clock output of $1^{\text {st }}$ flip-flop should be 'O'. (Because input of $2^{\text {nd }}$ flip-flop is connected to $\bar{Q}$ ) and after applying clock output of $1^{\text {st }}$ flip- flop should be '1'. And it depends only upon input data when it changes from '0' to '1'.

Q29GATE 2011MCQ

Two D flip-flops are connected as a synchronous counter that goes through the following $Q_{B}Q_{A}$ sequence 00 $\rightarrow$ 11 $\rightarrow$ 01 $\rightarrow$ 10 $\rightarrow$ 00 $\rightarrow$ .... The combination to the inputs $D_A \; and \; D_B$ are

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📖 Explanation

\begin{array}{cccc} \text { Present } & \text { State } & \text { Next } & \text { State } \\ Q_{B} & Q_{A} & Q_{B} & Q_{A} \\ 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 1 \\ 0 & 1 & 1 & 0 \\ 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 \end{array}

Now using excitation table of D flip-flop

\begin{aligned} D_{A}&=\left(Q_{A} Q_{B}+\bar{Q}_{A} \bar{Q}_{B}\right) \\ D_{B}&=\bar{Q}_{B} \end{aligned}

Q30GATE 2010MCQ

Assuming that the flip-flop are in reset condition initially, the count sequence observed at $Q_{A}$ , in the circuit shown is

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📖 Explanation

\begin{array}{ll} \text { Initially, } & Q_{A}=Q_{B}=Q_{C}=0 \\ & D_{A}=Q_{B} \odot Q_{C}=1, D_{B}=Q_{A}=0 \\ & D_{C}=Q_{B}=0 \end{array}

After one clock pulse,

\begin{array}{l} Q_{A}=1, Q_{B}=0, Q_{C}=0\\ D_{A}=Q_{B} \odot Q_{C}=1 \\ D_{B}=Q_{A}=1, D_{C}=Q_{B}=0 \end{array}

After two clock pulse,

\begin{array}{l} Q_{A}=1, Q_{B}=1, Q_{C}=0\\ D_{A}=Q_{B} \odot Q_{C}=0 \\ D_{B}=Q_{A}=1, D_{C}=Q_{B}=1 \end{array}

After three clock pulses,

\begin{array}{l} Q_{A}=0, Q_{B}=1, Q_{C}=1 \\ D_{A}=Q_{B} \odot Q_{C}=1 \\ D_{B}=Q_{A}=0, D_{C}=Q_{B}=1 \end{array}

After four clock pulse,

\begin{array}{l} Q_{A}=1, Q_{B}=0, Q_{C}=1\\ D_{A}=Q_{B} \odot Q_{C}=0 \\ D_{B}=Q_{A}=1, D_{C}=Q_{B}=0 \end{array}

After five clock pulse,

\begin{array}{l} Q_{A}=0, Q_{B}=1, Q_{C}=0\\ D_{A}=Q_{B} \odot Q_{C}=0 \\ D_{B}=Q_{A}=0, D_{C}=Q_{B}=1 \end{array}

After six clock pulse, $Q_{A}=0, Q_{B}=0, Q_{C}=1$ Therefore, the count sequence observed at $Q_{A}$ is $0110100 \ldots \ldots$

Q31GATE 2009MCQ

What are the counting states ( $Q_1,Q_2$ ) for the counter shown in the figure below

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📖 Explanation

\begin{array}{ccccccc}\text { Clock } & J_{1} & K_{1} & J_{2} & K_{2} & Q_{1} & Q_{2} \\ 0 & 1 & 1 & 1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ 2 & 0 & 0 & 0 & 1 & 1 & 0 \\ 3 & & & & & & \end{array}

So the sequence is 11,10,00,11,10,00 ....

Q32GATE 2009MCQ

Refer to the NAND and NOR latches shown in the figure. The inputs ( $P_1,P_2$ ) for both latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs ( $Q_1,Q_2$ ) are

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📖 Explanation

For NAND gates: Inputs $[(0,1) ;(1,1)]$ $\Rightarrow$ Output $[(1,0) ;(1,0)]$ For NOR gates: Inputs $[(0,1) ;(1,1)]$ $\Rightarrow$ Output $[(1,0) ;(0,0)]$

Q33GATE 2008MCQ

For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible. Which of the following statements is true

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Q34GATE 2008MCQ

For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is $\bigtriangleup$ T. Which of the following wave forms correctly represents the output at $Q_1$ ?

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📖 Explanation

Time period of waveform of output at $Q_{1}=2 \times 2 \times T=4 T$ time at output Delay $Q_{1}=2 \Delta T$ Note: (i) Incase of n flip-flops in such case, Time period of last output waveform $=2^{n} T$ where, T= Time period for clock pulse (ii) Delay time $=n \Delta T$ where, $\Delta T=$ Propagation delay provided by one flip-flop

Q35GATE 2007MCQ

The following binary values were applied to the X and Y inputs of NAND latch shown in the figure in the sequence indicated below : X=0, Y=1; X=0, Y=0; X=1, Y=1. The corresponding stable P,Q output will be.

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Q36GATE 2007MCQ

For the circuit shown, the counter state ( $Q_1Q_0$ ) follows the sequence

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Q37GATE 2006MCQ

Two D-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following sequence $00 \rightarrow 01 \rightarrow 11 \rightarrow 10 \rightarrow 00 ...$ The inputs D0 and D1 respectively should be connected as,

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📖 Explanation

\begin{array}{cccc} Q_{1} & Q_{0} & D_{1}\left(Q_{0}\right) & D_{0}\left(\bar{Q}_{1}\right) \\ 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 1 \\ 1 & 1 & 1 & 0 \\ 1 & 0 & 0 & 0 \end{array}

Q38GATE 2006MCQ

For the circuit shown in figures below, two 4 - bit parallel - in serial - out shift registers loaded with the data shown are used to feed the data to a full adder. Initially, all the flip - flops are in clear state. After applying two clock pulse, the output of the full-adder should be

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📖 Explanation

\begin{array}{lllllll} &A&B&C_{i}&S&C_{o}\\ \text { After } 2^{\mathrm{nd}} \mathrm{CP} & 1 & 1 & 0 & 0 & 1\\ \text { After } 2^{\mathrm{nd}} \mathrm{CP} & 1 & 1 & 1 & 1 & 1 \end{array}

Q39GATE 2005MCQ

The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is $Q_{2}Q_{1}Q_{0}$ = 011 then is next state $Q_{2}Q_{1}Q_{0}$ will be

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📖 Explanation

\begin{aligned} \mathrm{Q}_{2} \mathrm{Q}_{1} \mathrm{Q}_{0}&=011 \\ \text { 1st } \mathrm{Clk} \rightarrow \mathrm{Q}_{2} \mathrm{Q}_{1} \mathrm{Q}_{0}&=100 \\ \mathrm{Q}_{0}&=1 \left(\text { triggers } T_{1}\right) \\ \bar{Q}_{1} &=1 \left(\text { triggers } T_{1}\right) \end{aligned}

Q40GATE 2005MCQ

The present output $Q_{n}$ of an edge triggered JK flip-flop is logic 0. If J = 1, then $Q_{n+1}$

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📖 Explanation

since $J=1$ and $Q_{n}=0 So Q_{n+1}=1$ as even if $K=0, Q_{n+1}=1 (set)$ and if $K=1, Q_{n+1}=\overline{Q_{n}}=1(\text { toggle })$