Q41GATE 2004MCQ

In the modulo-6 ripple counter shown in figure, the output of the 2- input gate is used to clear the J-K flip-flop. The 2-input gate is

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📖 Explanation

At the end of 6 th pulse all states should be cleared. $C B A=110 \quad \bar{C} \bar{B} X=00 X$ Output of desired gate should be zero as clear is given active low. So given gate should be OR as OR gate output is zero if both inputs are 0.

Q42GATE 2004MCQ

A master - slave flip flop has the characteristic that

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Q43GATE 2004MCQ

Choose the current one from among the alternative A,B,C,D after matching an item from Group 1 with the most appropriate item in Group 2.

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Q44GATE 2003MCQ

A 0 to 6 counter consists of 3 flip flops and a combination circuit of 2 input gate(s). The common circuit consists of

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Q45GATE 2003MCQ

A 4 bit ripple counter and a bit synchronous counter are made using flip flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

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📖 Explanation

Prop. delay of 4 bit ripple counter $R=4 \times t_{p d}=40 \mathrm{ns}$ In synchronous counter all flip-flops are given clock simultaneously so $S=10 \mathrm{ns}$

Q46GATE 2001MCQ

For the ring oscillator shown in figure, the propagation delay of each inverter is 100 pico second. What is the fundamental frequency of the oscillator output?

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📖 Explanation

$t_{P d}$ of all 5 intervals $=5 \times 100 \mathrm{p} \mathrm{sec}=500 \mathrm{p} \mathrm{sec}$ $\therefore$ fundamental frequency of oscillator $\text { Output }=\frac{1}{2 \times 500 \mathrm{ps}}=1 \mathrm{GHz}$

Q47GATE 2001MCQ

The digital block in figure is realized using two positive edge triggered D-flip-flops. Assume that for $t \lt t_{0}$ , $Q_{1}$ = $Q_{2}$ =0. The circuit in the digital block is given by:

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