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GATE EE · Digital Electronics

Microprocessors Practice Questions

Generate GATE-level questions on 8085 Microprocessor. Focus on: 1. Architecture, Register organization, and Flag register. 2. Instruction set: Addressing modes and Machine cycles. 3. Interrupts, Memory and I/O interfacing.

23 questions · 20 PYQs · 0 AI practice · GATE EE 2027

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Q1GATE 2023NAT

In a given 8-bit general purpose micro-controller there are following flags. C-Carry, A-Auxiliary Carry, O-Overflow flag, PParity ( 0 for even, 1 for odd) R0 and R 1 are the two general purpose registers of the microcontroller. After execution of the following instructions, the decimal equivalent of the binary sequence of the flag pattern [CAOP] will be MOV R0, +0x60 MOV R1, +0x46 ADD R0, R 1

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📖 Explanation

MOV $R_{0},+0 \times 60 \Rightarrow R_{0} \leftarrow 60 \mathrm{H}$ MOV $R_{1},+0 \times 46 \Rightarrow \mathrm{R}_{1} \leftarrow 46 \mathrm{H}$ ADD $R_{0}, R_{1}$ :

\begin{array}{lllllllll} 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & \rightarrow 46 \mathrm{H} \\ \hline 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & \rightarrow \mathrm{A} 6 \mathrm{H} \\ \hline \end{array}

Now, carry flag $(C Y)=0$ Auxiliary carry $(\mathrm{AC})=0$ $\left[\because\right.$ No carry fro $D_{3}$ to $\left.D_{4}\right]$ $\because \mathrm{MSB}=1$ , overflow flag $=1$ $P=0[\because$ Four 1's i.e. even numb er $]$ $\therefore$ Required Flag patter $=[$ CAOP $]$ $=[0010]_{2}=2$

Q2GATE 2020NAT

An 8085 microprocessor accesses two memory locations (2001 H) and (2002H), that contain 8-bit numbers 98H and B1H respectively. The following program is executed: LXI H, 2001 H MVIA, 21H INX H ADD M INX H MOV M, A HLT At the end of this program, the memory location 2003H contains the number in decimal (base 10) form ________

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📖 Explanation

\begin{aligned} LXI H, 2001 H & \rightarrow [HL] \rightarrow 2001 H \\MVI A, 21 H & \rightarrow [A] \leftarrow 21 H \\INX H & \rightarrow [HL] \rightarrow 2002 H \\ ADD M & \rightarrow [A] + [2002] \rightarrow [A] \\ &= (21H + B1 H) \rightarrow [A] \\ &= D2 H \rightarrow [A] \\ INX H & \rightarrow [HL] \rightarrow 2003 H \\ MOV M, A & \rightarrow [2003] \leftarrow [A] \\ [2003] &= D2 H = (1101\; 0010)_2 \\ &= 1 \times 2^{7+}1\times 2^{6+}1\times 2^4 +1\times 2^1 \\&= 128 + 64 + 16 + 2 \\&= 210 \end{aligned}

Q3GATE 2014MCQ

In an 8085 microprocessor, the following program is executed At the end of program, register A contains

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📖 Explanation

For the RAR operation and $B\leftarrow 04$ Similarly for each RAR operation the content of B is decremented by '1' till it becomes 00H. Thus, $B\leftarrow 04\;\; A\leftarrow 00000011$ $B\leftarrow 03\;\; A\leftarrow 10000001$ $B\leftarrow 02\;\; A\leftarrow 11000000$ $B\leftarrow 01\;\; A\leftarrow 01100000 B\leftarrow 00$ Therefore, at the end of the program, egister 'A' contains 60H.

Explanation Figure 2

Explanation Figure 3

Q4GATE 2014MCQ

An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is shown in figure The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enables lines $E_1,\bar{E_2},\bar{E_3}$ . The address of the device is

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📖 Explanation

For the given decoder $E-=A_{12}\bar{A_{11}}=1 (enable)$ $\therefore \;\; A_{12}$ should be HIGH and $A_{11}$ should be LOW. Also, $E_2=E_3=0(disable)$ The decoder output depends on $I_2=A_{15}, I_1=A_{14}$ and $I_0=A_{13}$ which should be 010 respectively to enable the output port. The address of the device is 5000H-57FFH,

Q5GATE 2014MCQ

In 8085A microprocessor, the operation performed by the instruction LHLD 2100H is

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📖 Explanation

Currently no explanation available

Q6GATE 2011MCQ

A portion of the main program to call a subroutine SUB in an 8085 environment is given below. : : LXI D, DISP LP : CALL SUB : : It is desired that control be returned to LP+DISP+3 when the RET instruction is executed in the subroutine. The set of instructions that precede the RET instruction in the subroutine are

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📖 Explanation

Call takes 3 address locations, RET always returns to LP+3 location, this stored in SP. So to return to LP+DISP+3. We have to add DISP to SP. POP H DAD D PUSH H Normal call operation shown.

Explanation Figure 2

Q7GATE 2010MCQ

When a "CALL Addr" instruction is executed, the CPU carries out the following sequential operations internally : Note: (R) means content of register R ((R)) means content of memory location pointed to by R. PC means Program Counter SP means Stack Pointer

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📖 Explanation

First of all content of PC is loaded into stack i.e. address of next instruction to be executed is loaded onto stack. i.e. SP is decremented then PC is loaded by address given in call instruction.

Q8GATE 2009MCQ

The increasing order of speed of data access for the following device is (I) Cache Memory (II) CD-ROM (III) Dynamic RAM (IV) Processor Registers (V) Magnetic Tape

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📖 Explanation

Access time of the residter is very less than that from a memory access. So speed of data access is faster in case of processor register. Second highest is cache memory because it's size is small, so searching of data takes less time.

Q9GATE 2009MCQ

In an 8085 microprocessor, the contents of the Accumulator, after the following instructions are executed will become XRA A MVI B, F0 H SUB B

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📖 Explanation

Currently no explanation available

Q10GATE 2008MCQ

An input device is interfaced with Intel 8085A microprocessor as memory mapped I/O. The address of the device is 2500H. In order to input data from the device to accumulator, the sequence of instructions will be

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📖 Explanation

Currently no explanation available

Q11GATE 2008MCQ

The content of some of the memory location in an 8085 accumulator based system are given below The content of stack (SP), program counter (PC) and (H,L) are 2700H, 2100H and 0000H respectively. When the following sequence of instruction are executed. 2100 H: DAD SP 2101 H: PCHL the content of (SP) and (PC) at the end of execution will be

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📖 Explanation

Given, (SP) = 2700H (PC)=2100H (HL)=0000H 2100H : DAD SP (SP) +(HL) $\rightarrow$ (HL) 2700H +0000H =2700H stored in HL pair. 2101H : PCHL : the content of HL are transferred to (PC) So, now (PC) =2700H and (SP) also unchanged (PC)=2700H (SP)=2700H

Q12GATE 2007MCQ

The associated figure shows the two types of rotate right instructions $R_1,R_2$ , available in a microprocessor where Reg is a 8-bit register and C is the carry bit. The rotate left instructions $L_1 \; and \;L_2$ are similar except that C now links the most significant bit of Reg instead of the least significant one. Such a division can be correctly performed by the following set of operatings

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📖 Explanation

Currently no explanation available

Q13GATE 2007MCQ

The associated figure shows the two types of rotate right instructions R_1, R_2, available in a microprocessor where Reg is a 8-bit register and C is the carry bit. The rotate left instructions L1 and L2 are similar except that C now links the most significant bit of Reg instead of the least significant one. Suppose Reg contains the 2's complement number 11010110. If this number is divided by 2 the answer should be

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📖 Explanation

Currently no explanation available

Q14GATE 2007MCQ

Which one of the following statements regarding the INT (interrupt) and the BRQ (but request) pins in a CPU is true?

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📖 Explanation

Currently no explanation available

Q15GATE 2006MCQ

A software delay subroutine is written as given below : DELAY : MVI H, 255D MVI L, 255D LOOP : DCR L JNZ LOOP DCR H JNZ LOOP How many times DCR L instruction will be executed ?

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📖 Explanation

First of all DCR L will be executed for 255 times till content of L becomes 0. After that for every decrement of H it will be executed 256 times ( first when L is decremented by 1 and becomes $FF_H$ and then $FF_H=255_D$ times ) and this will be happen till content of H become 1 i.e. 254 times. So, overall it will be executed =255 + 254 x 256 =65279

Q16GATE 2006MCQ

In an 8085 A microprocessor based system, it is desired to increment the contents of memory location whose address is available in (D,E) register pair and store the result in same location. The sequence of instruction is

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📖 Explanation

The address of the memory location is stored in DE register pair. But, INR M command will increase the content of memory location M. but this command will execute only for HL pair. So, we have to exchange the address of memory location in HL pair from DE pair first.

Q17GATE 2005MCQ

The 8085 assembly language instruction that stores the content of H and L register into the memory locations $2050_{H}$ and $2051_{H}$ , respectively, is:

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📖 Explanation

Instruction $SHLD \;\;2050_H$ stores the content of L to memory location $2050_H$ and content of H to next memory location $2051_H$ .

Q18GATE 2004MCQ

If the following program is executed in a microprocessor, the number of instruction cycle it will take from START to HALT is

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📖 Explanation

Currently no explanation available

Q19GATE 2003MCQ

When a program is being executed in an 8085 Microprocessors, its Program Counter contains

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📖 Explanation

Program counter contains the memory address of the instruction that is to be executed next.

Q20GATE 2003MCQ

A memory system has a total of 8 memory chips, each with 12 address lines and 4 data lines, The total size of the memory system is

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📖 Explanation

Total size of memory = No. of chip x data lines $= 4 \times 8 \times 2^{12}$ =128 kbits =16 kbyte

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