Q2GATE 2021MCQ

A counter is constructed with three D flip-flops. The input-output pairs are named $(D_{0},\:Q_{0}), (D_{1},\:Q_{1})$ and $(D_{2},\:Q_{2})$ , where the subscript 0 denotes the least significant bit. The output sequence is desired to be the Gray-code sequence $000, \:001, \:011,\: 010, \:110,\:111,\: 101$ and $100$ , repeating periodically. Note that the bits are listed in the $Q_{2}\:Q_{1}\:Q_{0}$ format. The combinational logic expression for $D_{1}$ is

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📖 Explanation

$D_{1}=\bar{Q}_{2} Q_{0}+Q_{1} \bar{Q}_{0}$

Q3GATE 2016MCQ

Consider the following circuit which uses a 2-to-1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of A and B is

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📖 Explanation

In the given multiplexer, $I=0=\bar{A}, I_1=A$ $Select =B$ $F=\bar{B}I_0+BI_1$ $F=\bar{B}\bar{A}+AB=\overline{A\oplus B}$

Q4GATE 2015MCQ

In the 4 x 1 multiplexer, the output F is given by $F=A\oplus B$ . Find the required input ' $I_{3}I_{2}I_{1}I_{0}$ '.

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📖 Explanation

$F=A\oplus B$ $\;\;=\bar{A}B+A\bar{B}$ $\;\;=\bar{A}\bar{B}I_0+\bar{A}BI_1+A\bar{B}I_2+ABI_3$ $\Rightarrow \; I_0=0, I_1=1, I_2=1, i_3=0$ $I_3I_2I_1I_0=0110$

Q5GATE 2015MCQ

A Boolean function f(A,B,C,D)= $\Pi$ (1,5,12,15) is to be implemented using an 8x1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs $S_2S_1S_0$ of the multiplexer respectively. Which one of the following options gives the correct inputs to pins 0,1,2,3,4,5,6,7 in order?

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📖 Explanation

Boolean function $f(A,B,C,D)=\Pi (1,5,12,15)$ is implemented with 8x1 MUX

Q6GATE 2014MCQ

A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is $000_2$ . The output is pulled high. The output of the circuit follows the sequence

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📖 Explanation

For

\begin{matrix} A_2 & A_1 & A_0 & S_0 & S_1\\ 0 & 0 & 0 & 0 & 0 \end{matrix}

MUX is enabled and output is $I_0$ For

\begin{matrix} A_2 & A_1 & A_0 & S_0 & S_1\\ 0 & 0 & 1 & 0 & 0 \end{matrix}

MUX is disable and output is '1' similarly, for

Q7GATE 2012MCQ

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

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📖 Explanation

\begin{matrix} A & B & No. of cases\\ 01 & 00 & 1\\ 10 &00,01 &2 \\ 11 &00,01,10 &3\\ & & total=6 \end{matrix}

Q8GATE 2008MCQ

A 3-line to 8-line decoder, with active low outputs, is used to implement a 3-variable Boolean function as shown in the figure The simplified form of Boolean function F(A,B,C) implemented in 'Product of Sum' form will be

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📖 Explanation

Let us consider active high input $F=\Sigma (1,3,5,6)=\Pi M(0,2,4,7)$ $\;\;=(Y+Z)\cdot (X+Z)\cdot (\bar{X}+\bar{Y}+\bar{Z})$

Q9GATE 2006MCQ

A $\left ( 4\times 1 \right )$ MUX is used to implement a 3-input Boolean function as shown in figure. The Boolean function F(A,B,C) implemented is

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📖 Explanation

$F(A,B,C)=A\bar{B}\bar{C}+\bar{A}\bar{B}C+B\bar{C}$ $\;\;\;\;=\Sigma (1,2,4,6)$

Q10GATE 2003MCQ

Figure shows a 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with input bits P and Q and the carry input Cin. Which of the following combinations of inputs to $I_0, I_1, I_2$ and $I_3$ of the MUX will realize the sum S ?

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📖 Explanation

For a 4:1 mux $F=I_0\bar{A}\bar{B}+I_1\bar{A}B+I_2A\bar{B}+I_3AB$ where sum of full adder is $=A\oplus B\oplus C$ Truth table of Full adder

Q11GATE 2001MCQ

The output f of the 4-to-1 MUX shown in figure is

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📖 Explanation

$\because \;\;F=\Sigma min(1,2,3)$ $\therefore \;\; F=\bar{X}Y+X\bar{Y}+XY =X+\bar{X}Y=X+Y$

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