Fet And Mosfet Analysis Practice Questions

What is the voltage $V_{out}$ in the following circuit?

In the circuit shown, both the enhancement mode NMOS transistors have the following characteristic: $k_{n}=\mu _{n} C_{ox}(W/L)=1 mA/V^{2};V_{TN}=1V$ . Assume that the channel length modulation parameter $\lambda$ is zero and body is shorted to source. The minimum supply voltage $V_{DD}$ (in volts) needed to ensure that transistor $M_{1}$ operates in saturation mode of operation is _______.

For the n-channel MOS transistor shown in the figure, the threshold voltage $V_{Th}$ is 0.8 V. Neglect channel length modulation effects. When the drain voltage $V_{D}$ = 1.6 V, the drain current $I_{D}$ was found to be 0.5 mA. If $V_{D}$ is adjusted to be 2 V by changing the values of R and $V_{DD}$ , the new value of $I_{D}$ (in mA) is

For the MOSFETs shown in the figure, the threshold voltage $|V_{t}|$ = 2 V and $K=\frac{1}{2}\mu C_{OX}(\frac{W}{L})=0.1 mA/V^{2}$ . The value of $I_{D}$ (in mA) is ____.

For the MOSFET $M_{1}$ shown in the figure, assume W/L=2, $V_{DD}$ =2.0 V, $\mu _{N}C_{OX}=100\mu A/V^{2}$ and $V_{TH}=0.5V$ . The transistor $M_{1}$ switches from saturation region to linear region when $V_{\in}$ (inVolts) is ____.

In a MOSFET operating in the saturation region, the channel length modulation effect causes

The small-signal resistance $\left ( i.e.,dV_{B}/dI_{D} \right )$ in $k\Omega$ offered by the n-channel MOSFET M shown in the figure below, at a bias point of $V_{B}=2V$ is (device data for M: device transconductance parameter $k_{N}=\mu _{n}{C}'_{OX}\left ( \frac{W}{L} \right )= 40\mu A/V^{2}$ , threshold voltage $V_{TN}=1V$ , and neglect body effect and channel length modulation effects)

In the CMOS circuit shown, electron and hole mobilities are equal, and M1 and M2 are equally sized. The device M1 is in the linear region if

In the circuit shown below, for the MOS transistors, $\mu _{n}C_{OX}=100\mu A/V^{2}$ and the threshold voltage $V_{T}$ = 1V. The voltage $V_{x}$ at the source of the upper transistor is

Consider for CMOS circuit shown, where the gate voltage $V_{G}$ of the n-MOSFET is increased from zero, while the gate voltage of the p -MOSFET is kept constant at 3 V. Assume, that, for both transistors, the magnitude of the threshold voltage is 1 V and the product of the trans-conductance parameter and the (W/L) ratio, i.e. the quantity $\mu C_{ox}(W/L)$ , is $1mA \cdot V^{-2}$ . Estimate the output voltage $V_{0} \; for \; V_{G}$ = 1.5 V.

Two identical NMOS transistors M1 and M2 are connected as shown below. $V_{bias}$ is chosen so that both transistors are in saturation. The equivalent $g_{m}$ of the pair is defied to be $\frac{\partial I_{out}}{\partial V_{i}}$ at constant $V_{out}$ . The equivalent $g_{m}$ of the pair is

For the circuit shown in the following figure, transistor M1 and M2 are identical NMOS transistors. Assume the M2 is in saturation and the output is unloaded. The current $I_{x}$ is related to $I_{bias}$ as

In the CMOS inverter circuit shown, if the trans conductance parameters of the NMOS and PMOS transistors are $k_{n}=k_{p}=\mu _{n} C_{ox}\frac{W_{n}}{L_{n}}=\mu_{p} C_{ox}\frac{W_{P}}{L_{p}}=40\mu A/V^{2}$ and their threshold voltages are $V_{THn}=|V_{THp}|=1V$ , the current $I$ is

An n-channel depletion MOSFET has following two points on its $I_{D}-V_{GS}$ curve: (i) $V_{GS}$ =0 at $I_{D}$ =12 mA and (ii) $V_{GS}$ =-6 Volts at $I_{D}$ =0 mA Which of the following Q point will given the highest trans conductance gain for small signals?

Given $r_{d}=20k\Omega , \; I_{DSS}=10mA, \; V_{p}=-8V.$ Transconductance in milli-Siemens (mS) and voltage gain of the amplifier are respectively

For an n-channel MOSFET and its transfer curve shown in the figure, the threshold voltage is

Given $r_{d}=20k\Omega , \; I_{DSS}=10mA, \; V_{p}=-8V.$ $Z_{i} \;and \; Z_{0}$ of the circuit are respectively

Given $r_{d}=20k\Omega , \; I_{DSS}=10mA, \; V_{p}=-8V.$ $I_{D} \; and \; V_{DS}$ under DC conditions are respectively