Semiconductor Electronics – NEET UG PhysicsPractice Questions & PYQs

The voltage gain of a common emitter amplifier is determined by the equation $A_V = \beta \frac{R_C}{R_B}$, combining the current amplification factor with the ratio of collector resistance to base resistance. Plugging in the given parameters gives $A_V = 100 \times \frac{2}{1} = 200$. Since voltage gain is also the ratio of output voltage to input voltage, the input signal voltage is obtained by dividing 4 V by 200, which results in 0.02 V or 20 mV.

The circuit functions as a three-input NAND gate, where the output is defined by the Boolean expression $Y = \overline{A \cdot B \cdot C}$. When inputs A, B, and C are all 0, the product term is 0, which inverts to give an output of 1. When all three inputs are switched to 1, the product term evaluates to 1, yielding an inverted output of 0.

Logic gate circuits are analyzed by determining the Boolean expression corresponding to the interconnection of individual gates from inputs to output. Substituting the input values $A = 1$, $B = 0$, and $C = 1$ into the circuit's Boolean function satisfies the logical conditions of the intermediate gates. This specific combination successfully drives the final gate's operation, resulting in the desired high output of $1$.

A p-n junction diode configured with a load resistor operates as a half-wave rectifier that permits current flow in a single direction. When the alternating 10 V square input signal is applied, the diode becomes forward-biased during the positive half-cycles to successfully deliver the voltage across the load. Conversely, the diode turns reverse-biased during the negative half-cycles and blocks the current, dropping the output to zero. This selective rectification yields an output waveform consisting exclusively of the positive rectangular pulses.

A common emitter amplifier introduces a phase reversal of $\pi$ radians between the input and output signals, meaning $180^\circ$ is added to the phase angle. The peak voltage of the output signal is determined by multiplying the input amplitude by the voltage gain, giving $150 \times 2 = 300$. Incorporating this new amplitude and the phase shift into the original trigonometric function yields the output signal equation $V_0 = 300 \cos \left(15 t + \frac{4\pi}{3}\right)$.

When a forward-biased diode is connected in a circuit, the net potential available across the external resistor is equal to the source e.m.f. minus the internal barrier potential of the diode. Subtracting the 0.5 V barrier voltage from the total 3.5 V source leaves a potential difference of 3.0 V across the resistor. Applying Ohm's law through the relation $I = \frac{V}{R}$, dividing this net voltage by the 100 ohm resistance yields a circuit current of 30 mA.

This combination relies on De Morgan's laws of Boolean algebra to evaluate the final output of sequentially inverted signals. When the initial inputs $A$ and $B$ pass through separate NOT gates, they produce intermediate states given by $y_1 = \overline{A}$ and $y_2 = \overline{B}$. Combining these inverted signals through a NOR gate results in the Boolean expression $y = \overline{y_1 + y_2}$, which simplifies directly to $y = A \cdot B$ to form an AND gate.

The barrier potential of a p-n junction is determined by the intrinsic properties of the semiconductor material itself, such as germanium or silicon, which dictate different band gaps. Additionally, the concentration of impurity atoms introduced during doping alters the internal electric field across the depletion region. Temperature fluctuations also impact the thermal generation of charge carriers, which directly influences the height of the potential barrier.

A solar cell generates electrical energy from light, and its output limits are defined by distinct open-circuit and short-circuit states. Under an open-circuit condition, the terminal current drops to zero ($I = 0$), causing the maximum potential to appear at point A as the open-circuit voltage. On the other hand, a short-circuit condition reduces the terminal potential to zero ($V = 0$), allowing the maximum charge flow to be measured at point B as the short-circuit current.

Doping an intrinsic semiconductor with group 15 elements introduces impurity atoms with five valence electrons, which donate extra conduction electrons into the crystal lattice. These thermally and impurity-generated electrons vastly outnumber the thermally created holes, rendering them the majority charge carriers. Consequently, the thermally excited vacancies left behind function as minority carriers within the material.

Logic gate operations are governed by Boolean algebra laws, notably the double inversion property which states that negating a signal twice brings it back to its original value, or $\overline{\overline{A}} = A$. Tracing the inputs through the circuit shows that input $A$ undergoes a double negation before meeting input $B$ at an AND gate, initially yielding $X = \overline{\overline{A}} \, \mathrm{B}$. Simplifying this expression using the fundamental inversion rule eliminates the double bars, resulting in a final output of $X = A \, \mathrm{B}$.

The voltage gain of a common emitter amplifier is directly proportional to the product of its transconductance and the output load resistance, expressed through the relation $A_v = g_m R_{out}$. For the initial configuration, substituting the given transconductance yields the first gain equation, while the second configuration provides a modified gain equation using the new transconductance value. Since the output load resistance remains unchanged, dividing the second equation by the first eliminates the resistance term. This establishes the direct ratio between the new voltage gain and the original gain $G$.

A NAND gate produces an output that is the inverted product of its inputs, expressed as $\overline{AB}$. When this signal is split into two parallel lines and fed into both inputs of a subsequent NAND gate, that second gate functions simply as an inverter. Mathematically, passing the first NAND output through this second inversion results in double negation, yielding $\overline{\overline{AB}} = A \cdot B$. This final Boolean expression defines the fundamental operation of an AND gate.

Transistors differ fundamentally in their doping types, which dictates the primary charge carriers injected across the emitter-base junction. Specifically, the emitter of an n-p-n transistor is doped with n-type material that injects free electrons into the base region. Conversely, the emitter of a p-n-p transistor consists of p-type material designed to inject holes into its respective base region.

Charge carrier diffusion across an unbiased p-n junction is driven purely by concentration gradients rather than external electric fields or terminal attractions. The p-type region contains an overwhelmingly high density of holes compared to the n-type region, creating a steep concentration gradient. This disparity naturally causes holes to migrate from the region of higher concentration in the p-side to the region of lower concentration in the n-side.

An OR gate produces a high output whenever at least one of its inputs is high, meaning a high state on any input terminal guarantees a high response. Tracking the voltage waveforms across the successive time frames reveals that the output $C$ stays low only when both inputs $A$ and $B$ are at 0, which occurs from 0 to $t_1$ and from $t_4$ to $t_5$. During all other intervals where at least one input rises to 1, the output $C$ correspondingly remains high, matching the characteristic truth table of this specific logic component.

The electrical behavior of group 14 elements depends heavily on the principal quantum shell occupied by their valence electrons. Carbon atoms house their four bonding electrons within the second atomic orbit, creating a tight nuclear bond that restricts free charge movement and results in wide band gaps typical of insulators. Conversely, silicon accommodates its bonding electrons in the third orbit, where increased atomic radius and shielding reduce nuclear attraction, allowing thermal energy to excite electrons into the conduction band more readily.

The logic circuit is governed by the Boolean expression $Y = (A+B) \cdot C$, which means the output depends on an OR operation combined with an AND gate. For the final output to reach $Y = 1$, the input $C$ must be high and the sub-expression $A+B$ must also evaluate to $1$.

Evaluating the combination where $A = 1$, $B = 0$, and $C = 1$ satisfies these exact requirements. Substituting these values into the expression produces $(1 + 0) \cdot 1$, which simplifies to $1 \cdot 1$ and successfully results in the desired output of $1$.

The collector current is found using Ohm's law via the relation $I_C = \frac{V_0}{R_C}$, which evaluates to 1 mA. Dividing this collector current by the current amplification factor gives the base current through the relation $I_B = \frac{I_C}{\beta}$. Finally, the input signal voltage is calculated by multiplying this base current by the base resistance using $V_i = I_B R_B$, resulting in 10 mV.

The voltage gain of a common emitter amplifier is governed by the relation $A_V = \beta \frac{R_L}{R_i}$, where the current gain $\beta$ is defined by the formula $\beta = \frac{\Delta I_C}{\Delta I_B}$. Substituting the given change in collector current of $2\text{ mA}$ and change in base current of $40\mu\text{A}$ yields a current gain of 50. Using this calculated current gain along with the load resistance of $4\text{ k}\Omega$ and input resistance of $100\mathrm{\Omega}$, the voltage gain evaluates to 2000.