Semiconductor Electronics – JEE Main PhysicsPractice Questions & PYQs

The energy released as a photon during electron-hole recombination in an LED is dictated by the band gap of the semiconductor material, expressed as $E_g = \frac{hc}{\lambda}$. Rearranging this to solve for the wavelength gives the equation $\lambda = \frac{hc}{E_g}$. By substituting the given band gap of 1.42 eV and the standard approximation of 1240 for the numerator, we perform the calculation $\lambda = \frac{1240}{1.42}$. This division results in an emitted wavelength of approximately 875 nm.

A NOR gate functions as the logical inverse of an OR gate, effectively combining an OR operation with a NOT inverter to produce its characteristic behavior. In this configuration, the Boolean expression is $Y = \overline{A + B}$, which indicates that the output remains logic high only when all inputs are at logic low, and it drops to logic low if any input is logic high. The presence of a small negation circle at the output terminal of the OR symbol is the defining feature that identifies this specific logic gate diagram.

Double negation in Boolean algebra allows us to simplify the expression $Y = \overline{\overline{(A+B)\cdot(AB)}}$ by canceling out the complementary bars, which yields $Y = (A+B)\cdot(AB)$. Distributing these terms reveals $Y = (A \cdot A \cdot B) + (B \cdot A \cdot B)$, which simplifies to $Y = AB + AB$ because $A \cdot A = A$ and $B \cdot B = B$. Since any variable added to itself results in the original variable, the expression reduces to $Y = A \cdot B$, confirming the circuit performs an AND operation.

When a p-n junction is forward biased, the applied external voltage opposes the built-in potential, lowering the barrier and enabling majority carriers to cross the junction, which makes the magnitude of the diffusion current far greater than the minority-carrier-dependent drift current. The direction of this conventional diffusion current is defined by the flow of positive charge, meaning it proceeds from the p-side to the n-side as holes cross into the n-region. Since the provided reason incorrectly identifies the direction of the diffusion current as being from the n-side to the p-side, it is false, even though the assertion correctly identifies the dominance of the diffusion current under forward bias.

A Light Emitting Diode is a specialized $p-n$ junction diode designed to emit radiation when charge carriers recombine across the junction. To facilitate this electroluminescence, the diode must be forward biased, which allows electrons from the $n$-region and holes from the $p$-region to move toward the depletion layer. During this recombination process, energy is released as photons, where the energy of the emitted light is typically equal to or slightly less than the forbidden energy gap $E_g$ of the semiconductor material. Since the device is specifically engineered to operate under forward bias, it does not function to emit light when subjected to a reverse bias, making the assertion that it emits light under reverse bias incorrect.

A NAND gate operates according to the Boolean expression $Y = \overline{A \cdot B}$, where the output level is LOW only when both input signals $A$ and $B$ are simultaneously at the HIGH logic level. By systematically evaluating the given input waveforms across each time interval, the output remains at the HIGH level for all conditions except where both $A$ and $B$ are HIGH, which results in the specific inverted pulse pattern shown in the correct option.

The operation of a transistor amplifier in common-emitter configuration relies on the current gain $\beta$, which defines the amplification factor between the base current and the collector current. To find the input base current, we first determine the collector current using the supply voltage and the load resistance in the collector branch, calculated as $I_C = \frac{V_{CC}}{R_C} = \frac{1\,\text{V}}{1\,\text{k}\Omega} = 1\,\text{mA}$. Given that the current gain $\beta$ is $100$, we apply the relationship $I_b = \frac{I_C}{\beta}$ to find the base current. Substituting the known values into this equation yields $I_b = \frac{1\,\text{mA}}{100} = 10\,\mu\text{A}$.

A Zener diode is specifically engineered to operate within its breakdown region when placed in reverse bias, which allows it to maintain a stable, constant voltage across its terminals despite fluctuations in the input supply or load current. Conversely, when the diode is forward-biased, it does not exhibit this breakdown characteristic and instead behaves exactly like a standard P-n junction diode. Consequently, the specialized utility of a Zener diode as a voltage regulator is strictly confined to reverse bias conditions, while forward biasing simply mirrors the behavior of a conventional semiconductor diode.

Doping silicon with trivalent Boron atoms produces a $P$-type semiconductor with an excess of holes, while doping with pentavalent Arsenic atoms results in an $N$-type semiconductor with an excess of electrons, confirming that the first statement is correct. Regarding the second statement, the formation of a $P$-$N$ junction generates a depletion region and an internal electric field directed from the $N$-side to the $P$-side, creating a barrier potential that halts the flow of majority charge carriers and ensures that no current registers on an externally connected ammeter unless an external bias voltage is applied.

As the temperature of a semiconductor rises, thermal energy excites more electrons from the valence band across the energy gap into the conduction band, directly causing the number of conduction band electrons ($n_{e}$) to increase. Because conductivity is proportional to the density of these charge carriers, this rise in $n_{e}$ leads to an increase in overall conductivity, which consequently causes the electrical resistance of the material to decrease.

A bipolar junction transistor is engineered with specific physical dimensions and impurity concentrations to ensure effective current control. The base region is intentionally kept the thinnest with minimum doping to minimize carrier recombination, while the collector is designed as the thickest segment with moderate doping to handle higher power dissipation, and the emitter is the most heavily doped region to maximize charge carrier injection. Since each part performs a distinct role requiring tailored electrical properties, the doping levels across the three regions are not the same, making the first statement false while confirming the second statement regarding size is entirely accurate.

A photodiode functions as a light-sensitive device where incident light generates a small photocurrent, and it is specifically operated in reverse bias because this mode maintains an extremely low background current, allowing the change in current resulting from illumination to be clearly detected. The statement regarding forward bias current being significantly larger than reverse bias current is also factually accurate for a standard p-n junction, as forward bias lowers the junction potential barrier to facilitate charge carrier flow, while reverse bias hinders this movement. However, this general diode characteristic does not define the reason for the reverse bias preference in photodiodes, which is rooted in the high sensitivity to proportional changes in current under light exposure rather than the absolute magnitude of the current in different bias states.

This circuit functions based on the principles of Boolean algebra and De Morgan's Laws, which allow for the reduction of logic gate combinations to their simplest form. Evaluating the signal flow through the circuit yields the output expression $Y = \overline{(\overline{a}+\overline{b})}$. Applying the properties of De Morgan's theorem demonstrates that this expression is equivalent to $\overline{\overline{(a \cdot b)}}$, which simplifies through double negation to the identity $Y = a \cdot b$. This resultant expression represents the specific operational behavior of an AND gate.

Semiconductors exhibit a unique electrical behavior where their resistivity decreases as the temperature rises, unlike metals which become more resistive. This relationship is described by the formula $\rho = \frac{m}{n e^{2} \tau}$, where $n$ represents the carrier concentration and $\tau$ is the relaxation time. Although an increase in temperature causes the relaxation time $\tau$ to decrease due to more frequent scattering, this effect is significantly overshadowed by the dramatic increase in the number of free charge carriers $n$ generated by thermal excitation, resulting in an overall drop in resistivity.

A NAND gate operates by performing an AND operation on the inputs and then inverting the result, meaning it yields a low output only when both input signals are simultaneously high. Mathematically, this behavior is represented as $Y = \overline{A \cdot B}$, ensuring that for any other combination of inputs, the output remains logic high. This distinct inverse relationship compared to an AND gate is what identifies the circuit as a NAND gate.

Diodes function as unidirectional switches where a forward-biased diode behaves as a resistor with a value of 25 ohms, while a reverse-biased diode acts as an open circuit with infinite resistance. By examining the polarity of the circuit, $D_2$ is identified as reverse-biased, which prevents any current flow through its branch. Consequently, the total current $I_1$ is forced to flow through the remaining forward-biased diodes $D_1$ and $D_3$, splitting equally between the conducting branches to yield the relationship $I_1 = 2I_2$, resulting in a ratio of $\frac{I_1}{I_2}=2$.

Determining the total current requires identifying which branches of the circuit are active based on the bias of the diodes. Because $D_1$ and $D_3$ are forward-biased, they function as conductive paths, while $D_2$ is reverse-biased and behaves like an open switch that prevents current flow through its branch. This simplifies the network into two resistors connected in parallel, leading to an equivalent resistance of $R_{\text{eq}} = \frac{20 \times 10}{20 + 10} = \frac{20}{3} \; \Omega$. Finally, dividing the battery voltage of $10 \; \text{V}$ by this equivalent resistance results in a current of $I = \frac{10}{\left(\frac{20}{3}\right)} = 1.5 \; \text{A}$.

The Fermi level acts as a critical energy benchmark, representing the state where the probability of electron occupancy is exactly 50% at absolute zero temperature. For an intrinsic semiconductor, the electron concentration equals the hole concentration, which forces the Fermi level to reside at the middle of the bandgap, defined by $E_F \approx \frac{E_c + E_v}{2}$. When we introduce donor impurities to create an n-type semiconductor, the abundance of electrons shifts the Fermi level upward toward the conduction band to accommodate the increased density of states. In contrast, doping with acceptor impurities to form a p-type semiconductor increases the hole concentration, pulling the Fermi level downward toward the valence band, while in metals, the overlapping bands ensure the Fermi level resides directly within the conduction band where states are available.

When a NAND gate has its inputs tied together, it effectively acts as a NOT gate, transforming input $A$ into $\overline{A}$ and input $B$ into $\overline{B}$. The final stage consists of another NAND gate that processes these inverted signals, producing an output defined by $\overline{\overline{A} \cdot \overline{B}}$. By applying Boolean algebraic laws, specifically De Morgan's theorem, this expression simplifies to $A + B$, indicating that the entire circuit performs the function of an OR gate.

The logical operation of the circuit is defined by the expression $Y = \overline{\overline{A} \cdot B}$, which simplifies using De Morgan's laws to $Y = A + \overline{B}$. This indicates the output behaves like an OR gate receiving the signal $A$ and the inverted signal $\overline{B}$. Applying these inputs to the expression confirms the circuit's behavior across all time intervals. Between $t_1$ and $t_2$, inputs $A=0$ and $B=1$ yield $0 + \overline{1} = 0$, while the interval from $t_2$ to $t_3$ with $A=1$ and $B=1$ results in $1 + \overline{1} = 1$. The period from $t_3$ to $t_4$ uses inputs $A=0$ and $B=0$, producing $0 + \overline{0} = 1$. In the intervals $t_4$ to $t_5$ where $A=1$ and $B=1$, and $t_5$ to $t_6$ where $A=1$ and $B=0$, the outputs are $1 + \overline{1} = 1$ and $1 + \overline{0} = 1$ respectively. After $t_6$, with $A=0$ and $B=0$, the output calculation $0 + \overline{0} = 1$ remains consistent with the established logic.