Semiconductor Electronics – JEE Main PhysicsPractice Questions & PYQs

In a common emitter n-p-n transistor amplifier, the output signal exhibits a phase reversal relative to the input because the configuration functions as an inverting amplifier. When the input voltage increases, it causes the base current $i_b$ to rise, which in turn increases the collector current $i_c$ due to the transistor's amplification properties. This rise in collector current causes a larger voltage drop across the collector resistor $R_c$, which forces the output voltage to decrease, resulting in a phase difference of 180°.

The electrical conductivity of a semiconductor is determined by the total mobility of its charge carriers, calculated using the formula $\sigma = e(n_e \mu_e + n_h \mu_h)$. The contribution from electrons is found by calculating $5 \times 10^{18} \times 2.0 = 1 \times 10^{19}$, and the contribution from holes is $5 \times 10^{19} \times 0.01 = 0.05 \times 10^{19}$. Summing these terms results in a total carrier factor of $1.05 \times 10^{19}$. Multiplying this by the electron charge constant $1.6 \times 10^{-19}$ C gives a final conductivity of 1.68 ($\Omega$-m)$^{-1}$.

Achieving a desired logic output of 1 depends entirely on satisfying the truth table requirements for every gate within the circuit. Since the circuit structure relies on an OR gate, its output must necessarily be 1, which happens whenever at least one of its primary inputs is high. By testing the condition $c=1$ alongside the input values $a=1$ and $b=0$, we satisfy the requirements of the OR gate, thereby ensuring the final system output reaches the target state.

The input characteristic of a transistor in a common emitter configuration behaves fundamentally like a forward-biased diode, where the input current increases exponentially with the applied input voltage. The input resistance is defined as $R_i = \frac{\Delta V_i}{\Delta I_i}$, meaning its reciprocal, $\frac{1}{R_i}$, corresponds to the slope of the input characteristic curve, or $\frac{dI_i}{dV_i}$. Because the exponential growth of the input current causes the curve to become increasingly steep at higher voltages, the slope-and thus the reciprocal of the input resistance-rises continuously as the input voltage increases.

The current gain $\beta$ in a common emitter configuration is defined as the ratio of collector current to base current, whereas the current gain $\alpha$ in a common base configuration represents the ratio of collector current to emitter current. Given that the total emitter current is the sum of base and collector currents, $I_E = I_B + I_C$, these parameters are related by the fundamental identity $\alpha = \frac{\beta}{1+\beta}$, which can be rearranged into the equivalent form $\frac{1}{\alpha} = \frac{1}{\beta} + 1$. Because these expressions accurately derive from the physical laws of transistor operation, the relationship $\alpha = \frac{\beta^2}{1+\beta^2}$ is mathematically and physically inconsistent with the standard definitions of current gain.

For metallic conductors such as copper, electrical resistance increases linearly with temperature because heightened thermal vibrations scatter charge carriers more frequently, which impedes their flow. In contrast, the resistance of an intrinsic semiconductor like undoped silicon decreases exponentially as temperature rises because thermal energy promotes more electrons across the band gap, significantly increasing the concentration of available charge carriers. This physical behavior is modeled by expressions like $\rho = \rho_0 e^{-aT}$, illustrating how the material's conductivity improves rapidly with added thermal activation.

To identify a transistor, one must recognize that a $pnp$ device features an $n$-type base situated between two $p$-type regions. When the positive lead of a multimeter connects to the $n$-type base and the negative lead attaches to a $p$-type terminal, the resulting PN junction is reverse-biased. Because a reverse-biased PN junction naturally presents high resistance to current flow, this specific configuration yields a high resistance measurement.

Transistors rely on a significant disparity between their input and output resistances to effectively amplify signals. The input circuit typically operates under forward bias, resulting in a low resistance $r_i$, whereas the output circuit operates under reverse bias, leading to a much higher resistance $r_0$. Evaluating the ratio $R = \frac{r_0}{r_i}$ reveals that this relationship consistently falls within the range of 1 to 10.

A Zener diode circuit with a series resistance $R = 100 \Omega$ and a maximum power dissipation of $1 \text{ W}$ operates based on the power equation $P = (V - IR)I$, where $V$ is the source voltage and $I$ is the current. This relationship, when substituted with the given values, results in the equation $V I - 100 I^2 = 1$, which can be rearranged into the quadratic form $100 I^2 - V I + 1 = 0$.

Since the operating current $I$ must be a real value for the circuit to function, the discriminant of this quadratic equation, defined as $D = b^2 - 4ac$, must be greater than or equal to zero. Substituting the coefficients gives $V^2 - 4(100)(1) \geq 0$, which simplifies to $V^2 \geq 400$ and yields a requirement of $V \geq 20 \text{ V}$. Because the source voltage must reach at least $20 \text{ V}$ to satisfy these power constraints, the range $0 - 24 \text{ V}$ is the only suitable option among those provided.

Identifying a specific logic gate from a timing diagram involves comparing the state of the output $x$ against the combinations of inputs $a, b, c, d$. An OR gate functions such that the output remains high whenever at least one of its inputs is high, and it only produces a low output when all inputs are simultaneously at a low state. This pattern of behavior, where the logical sum of the inputs determines the output level, matches the characteristics required to identify the OR gate.

The identification of these semiconductor devices relies on their unique $I-V$ characteristic curves observed under varying electrical conditions. A simple junction diode exhibits a characteristic exponential forward bias current and minimal reverse current, whereas a Zener diode is defined by a sharp, constant breakdown voltage in the reverse bias region. A solar cell is distinguished by its operation in the fourth quadrant where it acts as a power source, and a light-dependent resistor shows a linear ohmic relationship where the conductance, or slope of the curve, increases in response to higher incident light intensity.

Logic gates operate by producing specific output levels based on the combination of input signals provided. In this table, the output remains low only when both inputs are zero, but switches to a high state whenever at least one input is set to one. This behavior, which follows the boolean expression $Y = A + B$, uniquely characterizes the operation of an OR gate.

The intensity of electromagnetic radiation spreading uniformly from a point source is defined as the power per unit area, which diminishes with the square of the distance from the source. Physically, this intensity also relates to the maximum strength of the electric field, known as the amplitude $E_0$, through the expression $I = \frac{1}{2} c \epsilon_0 E_0^2$.

By equating the intensity calculated from power, $I = \frac{P}{4\pi r^2}$, to the field amplitude formula, we can derive the relation $E_0 = \sqrt{\frac{2P}{4\pi r^2 c \epsilon_0}}$. Inserting the given values of power 0.1 W and distance 1 m, along with the physical constants for the speed of light and vacuum permittivity, the calculation simplifies to a result of 2.45 V/m.

A p-n junction diode is in a forward biased state when the p-type semiconductor material is connected to the positive terminal of an external power supply and the n-type material is connected to the negative terminal, establishing a condition where $V_p > V_n$. This connection creates an external electric field that opposes the diode's internal built-in electric field, thereby decreasing the width of the depletion region and lowering the potential barrier. Consequently, the resistance of the diode drops significantly, allowing majority charge carriers to cross the junction and facilitating current flow as depicted in the correct diagram.

Estimating the uncertainty in a dependent variable caused by an error in the independent variable relies on the concept of differentials, where the change in current $\Delta I$ is approximated by the product of the derivative $\frac{dI}{dV}$ and the voltage measurement error $\Delta V$. Given the standard diode current relation $I = e^{1000V/T} - 1$, the rate of change of current with respect to voltage is expressed as $\frac{dI}{dV} = \frac{1000}{T} e^{1000V/T}$.

At the specified operating point where $I = 5$ mA and $T = 300$ K, the relationship $5 = e^{1000V/T} - 1$ implies that the exponential term $e^{1000V/T}$ evaluates to $6$. Substituting this value and the temperature into the derivative formula yields $\frac{dI}{dV} = \frac{1000}{300} \times 6$, which simplifies to $20$ mA/V. Applying the measurement error of $\Delta V = 0.01$ V to this rate results in an error in current of $\Delta I = 20 \times 0.01 = 0.2$ mA.

An LED functions as a forward-biased p-n junction diode that remains non-conductive until the applied voltage exceeds a specific threshold. Beyond this point, the $I-V$ characteristic shows that the current increases exponentially with the voltage, which is directly responsible for the corresponding increase in light intensity. Consequently, the graphical representation exhibits a negligible current flow initially, followed by a sharp, nonlinear rise as the forward voltage crosses the threshold barrier.

In a diode detector, the RC circuit is designed to function as an envelope detector, requiring the capacitor to discharge rapidly enough to follow the modulation envelope without diagonal clipping. The maximum frequency of modulation, $f_m$, that can be accurately detected is limited by the circuit resistance $R$, capacitance $C$, and the modulation index $m$. This requirement is expressed by the relationship:

$f_m \leq \frac{1}{2\pi RC} \cdot \frac{\sqrt{1-m^2}}{m}$

Using the provided parameters of $R = 100 \times 10^3$ $\Omega$ and $C = 250 \times 10^{-12}$ F, the cutoff frequency component defined by $\frac{1}{2\pi RC}$ calculates to $6.37$ kHz. By substituting this value along with the modulation index $m = 0.6$ into the frequency limit formula, the maximum modulated frequency that can be successfully detected is $5.31$ kHz.

This configuration of four NAND gates acts as an Exclusive-OR (XOR) gate, defined by the Boolean expression $Y = A \cdot \overline{B} + B \cdot \overline{A}$. The circuit produces a low output whenever both input bits are identical and a high output whenever the inputs differ. Following this principle, the logic yields 0 for inputs 0 and 0, 1 for inputs 0 and 1, 1 for inputs 1 and 0, and 0 for inputs 1 and 1.

According to De Morgan's Law, passing two inverted inputs through a NAND operation results in an output that is logically equivalent to the sum of the original inputs $A$ and $B$. By representing the gate's output as $X = \overline{(\overline{A} \cdot \overline{B})}$, we apply the law to distribute the negation, yielding $X = \overline{\overline{A}} + \overline{\overline{B}}$, which simplifies directly to $A + B$. This final boolean expression confirms that the circuit functions as an OR gate.

The logic circuit effectively operates as an AND gate based on the logical expression $y = \overline{(\overline{A} + \overline{B})}$. By applying De Morgan's theorem, the expression simplifies to $y = \overline{\overline{A}} \cdot \overline{\overline{B}}$, which reduces to $y = A \cdot B$. Consequently, the output follows the standard AND gate truth table where a high output of 1 occurs exclusively when both input signals $A$ and $B$ are 1, while any combination involving at least one 0 input results in an output of 0.