What memory address range is NOT represents by chip # 1 and chip # 2 in the figure? in this figure are the address lines and CS means chip select.

Chip 1 Chip 2 cannot be the memory range for Chip #1 and Chip #2

GATE ECE · Microprocessor

Interfacing And Peripheral Devices – GATE ECE MicroprocessorPractice Questions & PYQs

Generate GATE-level questions on Interfacing and Peripheral Devices. Focus on: 1. Memory interfacing (RAM, EPROM). 2. I/O interfacing: 8255 PPI, 8254 Timer/Counter. 3. Data converters: ADC and DAC interfacing.

10 questions · 10 PYQs · 0 AI practice · GATE ECE 2027

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Q1GATE 2016MCQ

An 8 Kbyte ROM with an active low Chip Select input ( $\overline{CS}$ ) is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as $A_{15} \; to \; A_{0}, \; where \; A_{15}$ is the most significant address bit. Which one of the following logic expressions will generate the correct $\overline{CS}$ signal for this ROM?

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📖 Explanation

\begin{aligned} & \text {8kB ROM is given }\\ &\therefore 2^{n}=8 k B=2^{3}\left(2^{10}\right)=2^{13} \end{aligned}

$\therefore$ 13 Address lines are required for memory chip. But the address range given as 1000H-2FFF H In order to get $\overline{C S}$ as low, the condition is $A_{15}=A_{14}=0$ and $A_{13}=0 / 1, A_{12}=1 / 0$ The circuit to generate an active low chip select signal can be given as shown below: The logical expression can be written as,

\begin{aligned} F &=A_{15}+A_{14}+\left(A_{13} \odot A_{12}\right) \\ &=A_{15}+A_{14}+\left(A_{13} \cdot A_{12}+\bar{A}_{13} \cdot \bar{A}_{12}\right) \end{aligned}

Q2GATE 2015NAT

A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is _______.

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📖 Explanation

Memory size $=16 \mathrm{kB}=214 \mathrm{bits }$ Number of address lines = Number of data lines

\begin{aligned} 2^{n} \cdot 2^{n} &=2^{14} \\ \quad n &=7 \end{aligned}

Q3GATE 2014MCQ

For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data $(DI_{0}-DI_{7})$ h from an external device is shown in the figure. The instruction for correct data transfer is

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📖 Explanation

To transfer, the data should be present in accumulator and proper instruction should be executed. For the proper working, AND gates 1 and 2, should produce output as 1. Since $\bar{DS}_{1}$ , is connected to output 0 of decoder so input selection should be 000, therefore address lines have inputs as i.e. accumulator should be fed with the contents of address F8F8 H i.e. LOA F8F8 H.

\begin{aligned} A_{15} & A_{14}& A_{13}& A_{12}& A_{11}& A_{10}& A_{9}& A_{8} &A_{7} & A_{6}& A_{5}& A_{4} & A_{3} & A_{2}& A_{1}& A_{0} \\ 1&1&1&1&1&0&0&0&1&1&1&1&1&0&0&0 \end{aligned}

If $IO/\bar{M} =0$ ; to activate $\bar{G}_{2A}I/O$ is treated as M/M mapped I/O hence I/O has 16-bit address.

Q4GATE 2013MCQ

There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the figure below. RAMs 1, 2, 3 and 4 respectively are mapped to addresses

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📖 Explanation

Since the range of RAM # 1 is different in all the four options. So we will check for RAM 1 only and then the same procedure can be followed for RAM 2, 3 and 4. So, RAM # 1 will be selected when

\begin{array}{l} S_{0}=0 \\ S_{1}=0 \\ S_{0}=A_{12}=0 \\ S_{1}=A_{13}=0 \end{array}

Now the RAM # 1 will be enable when the input of MUX is 1, or the output of AND gate is 1.

\begin{aligned} \mathrm{SO}, & A_{10}=0 \\ A_{11} &=1 \\ A_{14} &=0 \\ A_{15} &=0 \end{aligned}

\begin{array}{cccc|cccc|cccc|cccc|c} A_{15} & A_{14} & A_{13} & A_{12} & A_{11} & A_{10} & A_{9} & A_{8} & A_{7} & A_{6} & A_{5} & A_{4} & A_{3} & A_{2} & A_{1} & A_{0} & \\ \hline 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & \text { Start } \\ 0 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & \text { End } \\ \hline 0 & & &&& 8 & & & 0 & & & &0 & &&&\text { Start } \\ 0& &&& & B& & & F& & & & F & & &&\text { End } \\ \hline \end{array}

So, range of RAM # 1 is 0800H to 0BFFH

Q5GATE 2010MCQ

In the circuit shown, the device connected Y5 can have address in the range

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📖 Explanation

$1O/\bar{M}$ =O to Activate G1 To select Y5, input CBA should be 101. Possible range will be

\begin{aligned} &A_{15} &A_{14} &A_{13} &A_{12} &A_{11}&A_{10} &A_{9} &A_{8} &A_{7}\ldots&A_{0} \\ &0 &0 &1 &0 &1 &1 &0 &1 &0\ldots&0 \\ &0 &0 &1 &0 &1 &1 &0 &1 &1\ldots&1 \\ \end{aligned}

Therefore, the device can have address in the range 2D00 H -2DFF H

Q6GATE 2007MCQ

An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as show in the figure. The address lines $A_0 \; and \; A_1$ of the 8085 are used by the 8255 chip to decode internally its thee ports and the Control register. The address lines $A_3 \; to \; A_7$ as well as the $IO/\bar{M}$ signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is

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📖 Explanation

As $\mathrm{A}_{2}$ is not shown, it can be O/1. O/P of NAND gate is 0 if $A_{7} \text{ to }A_{3} \& IO / \bar{M}=1$

\begin{aligned} &A_{7} &A_{6} &A_{5} &A_{4} &A_{3}\quad &A_{2} &A_{1} &A_{0} \\ \text{Starting Address }&1 &1 &1 &1 &1 &0 &0 &0 &\rightarrow \mathrm{F} 8 \mathrm{H}\\ \text{Final Address }&1 &1 &1 &1 &1 &1 &1 &1 &\rightarrow \mathrm{FFH} \end{aligned}

Q7GATE 2006MCQ

An I/O peripheral device shown in Fig. (b) below is to be interfaced to an 8085 microprocessor. To select the I/O device in the I/O address range D4H - D7H, its chip-select ( $\overline{CS}$ ) should be connected to the output of the decoder shown in figure (a) below :

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📖 Explanation

$\therefore$ Output taken from 5th

Q8GATE 2005MCQ

What memory address range is NOT represents by chip # 1 and chip # 2 in the figure? $A_{0} \; to \; A_{15}$ in this figure are the address lines and CS means chip select.

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📖 Explanation

Chip 1

\begin{array}{cccccccccccc}A_{15} & \ldots & \ldots & A_{12} & A_{11} & A_{10} & A_{9} & A_{8} & A_{7} & \ldots & \ldots & A_{0} \\ \times & \times & \times & \times & \times & \times & 0 & 1 & 0 & 0 & 0 & 0 \\ \times & \times & \times & \times & \times & \times & 0 & 1 & 1 & 1 & 1 & 1\end{array}

Chip 2

\begin{array}{cccccccccccc}A_{15} & \ldots & \ldots & A_{12} & A_{11} & A_{10} & A_{9} & A_{8} & A_{7} & \ldots & \ldots & A_{0} \\ \times & \times & \times & \times & \times & \times & 1 & 0 & 0 & 0 & 0 & 0 \\ \times & \times & \times & \times & \times & \times & 1 & 0 & 1 & 1 & 1 & 1\end{array}

$\therefore F800-F9FF$ cannot be the memory range for Chip #1 and Chip #2

Q9GATE 2004MCQ

The 8255 Programmable Peripheral Interface is used as described below. (i) An A/D converter is interface to a microprocessor through an 8255. The conversion is initiated by a signal from the 8255 on Port C. A signal on Port C causes data to be stobed into Port A. (ii) Two computers exchange data using a pair of 8255s. Port A works as a bidirectional data port supported by appropriate handshaking signals. The appropriate modes of operation of the 8255 for (i) and (ii) would be

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Q10GATE 2001MCQ

An 8085 microprocessor based system uses a 4K x 8-bit RAM whose starting address is AA00. The address of the last byte in this RAM is

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📖 Explanation

12 add. lines are present $4k = 2^{12}$

\begin{aligned} AA00&=1010 1010 0000 0000 \\ \text{Last Add }&= \frac{\quad 1111\quad 1111 \quad 1111\quad}{\frac{1011}{B}\quad\frac{1001}{B}\quad F\quad F} = B9FF \end{aligned}

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