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GATE ECE · Electronic Devices

Bjt And Fet Basics Practice Questions

Generate GATE-level questions on BJT and FET Basics. Focus on: 1. BJT physics: Current components, Gain, and Operating regions. 2. MOSFET basics: MOS capacitor, Threshold voltage, and Drain current equations. 3. JFET basics: Structure and Operation.

56 questions · 20 PYQs · 0 AI practice · GATE ECE 2027

Q21GATE 2016NAT

Consider an n-channel metal oxide semiconductor field effect transistor (MOSFET) with a gate-tosource voltage of 1.8V. Assume that $\frac{W}{L}=4$ , $\mu _{N}C_{ox}=70\times 10^{-6}AV^{-2}$ , the threshold voltage is 0.3V, and the channel length modulation parameter is 0.09 $V^{-1}$ . In the saturation region, the drain conductance (in micro seimens) is ________

🚀 Solve in Practice Mode

📖 Explanation

In the saturation region,

\begin{aligned} g_{d} &=\lambda I_{O S} \\ &=\lambda\left[\frac{1}{2} \mu_{n} C_{o x} \frac{w}{L}\left(V_{G S}-V_{T}\right)^{2}\right]\$ \\ &=0.09\left[\frac{1}{2} \times 70 \times 10^{-6} \times 4(1.8-0.3)^{2}\right]\$ \\ g_{d} &=28.35 \mu \mathrm{s} \end{aligned}

Q22GATE 2016MCQ

Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): P: As channel length reduces, OFF-state current increases. Q: As channel length reduces, output resistance increases. R: As channel length reduces, threshold voltage remains constant. S: As channel length reduces, ON current increases. Which of the above statements are INCORRECT?

🚀 Solve in Practice Mode

📖 Explanation

Currently no explanation available

Q23GATE 2016MCQ

A long-channel NMOS transistor is biased in the linear region with $V_{DS}$ =50 mV and is used as a resistance. Which one of the following statements is NOT correct?

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📖 Explanation

\begin{aligned} r_{ds} &=\frac{1}{\mu_{n} C_{01} \frac{W}{L}\left(V_{\mathrm{as}}-v_{r}\right)} \\ r_{ds} &=\text { channel resistance } \end{aligned}

\begin{array}{l} W \uparrow r \downarrow A \rightarrow \text { correct } \\ V_{T} \downarrow r \downarrow B \rightarrow \text { correct } \\ L \uparrow r \uparrow C \rightarrow \text { correct } \\ V_{\triangle} \uparrow r \downarrow \therefore D \rightarrow \text { Wrong statement } \end{array}

Q24GATE 2016NAT

Consider a long-channel NMOS transistor with source and body connected together. Assume that the electron mobility is independent of $V_{GS}$ and $V_{DS}$ . Given, $g_{m}=0.5 \mu A/V \; for \; V_{DS}=50mV \; and \; V_{GS}=2 V$ , $g_{d}=8 \mu A/V \; for \; V_{GS}=2V \; and \; V_{DS}=0 V$ , where $g_{m}=\frac{\partial I_{D}}{\partial V_{GS}}$ and $g_{d}=\frac{\partial I_{D}}{\partial V_{DS}}$ The threshold voltage (in volts) of the transistor is ________

🚀 Solve in Practice Mode

📖 Explanation

since $V_{G S} \gt V_{D S}$ MOSFET is in linear operation

\begin{aligned} I_{D} &=K_{N}^{\prime}\left[V_{G S}-V_{T}\right] V_{D S} \\ \frac{d I_{D}}{d V_{G S}} &=K_{N} V_{D S} \\ g_{m} &=K_{N}^{\prime} V_{D S} \\ 0.5 \times 10^{-6} &=K_{N}^{\prime}\left[50 \times 10^{-3}\right]\$ \therefore K_{N}^{\prime}=10^{-5} \\ I_{D} &=K_{N}\left[V_{G S}-V_{T}\right] V_{D S} \\ \frac{d I_{D}}{d V_{D S}} &=K_{N}\left[V_{G S}-V_{T}\right] \\ g_{d} &=K_{N}\left[V_{G S}-V_{T}\right] \\ 8 \times 10^{-6} &=10^{-5}\left[2-V_{T}\right] \\ \text { On solving } V_{T} &=1.2 \mathrm{V} \end{aligned}

Q25GATE 2015NAT

In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The permittivities of the semiconductor and the oxide layer are $\varepsilon_{s} \; and \;\varepsilon_{ox}$ respectively.Assuming $\varepsilon_{s} / \varepsilon_{ox} = 3$ , the ratio of the maximum capacitance to the minimum capacitance of this MOS capacitor is ________.

🚀 Solve in Practice Mode

📖 Explanation

\begin{aligned} \frac{C_{\max }}{C_{\min }}=& \frac{\frac{\epsilon_{O x}}{t_{O x}}}{\frac{E_{O x}}{t_{O x}} \times \frac{\epsilon_{S}}{X_{d m a x}}}=\left[1+\frac{X_{d \max }}{t_{o x}} \times \frac{\epsilon_{0 x}}{\epsilon_{s}}\right] \\ & \frac{\epsilon_{O x}}{t_{O x}}+\frac{\epsilon_{S}}{X_{d m a x}} \\ &=\left[1+\frac{100}{10} \times \frac{1}{3}\right]=4.33 \end{aligned}

Q26GATE 2015MCQ

For the NMOSFET in the circuit shown, the threshold voltage is $V_{th}$ , where $V_{th}$ > 0. The source voltage $V_{SS}$ is varied from 0 to $V_{DD}$ . Neglecting the channel length modulation, the drain current $I_{D}$ as a function of $V_{SS}$ is represented by

🚀 Solve in Practice Mode

📖 Explanation

$V_{G S}=V_{D S}$ Hence MOS transistor is in saturation. In saturation, $I_{D}=k\left(V_{G S}-V_{T}\right)^{2}=k\left(V_{D D}-V_{S S}-V_{T}\right)^{2}$ As, $V_{S S}$ increases $I_{D}$ decreases (Not linearly because square factor) Hence option (a) is correct.

Q27GATE 2015NAT

The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain-source voltage of 5 V. When the drain-source voltage was increased to 6 V while keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain to source saturation voltage is much smaller than the applied drain-source voltage. The channel length modulation parameter $\lambda$ (in $V^{-1}$ ) is _______.

🚀 Solve in Practice Mode

📖 Explanation

$\lambda=\frac{\Delta I_{D}}{I_{D} \Delta V_{D S}}=\frac{0.02 \mathrm{mA}}{1 \mathrm{mA} \times 1 \mathrm{V}}=0.02$

Q28GATE 2015MCQ

If the base width in a bipolar junction transistor is doubled, which one of the following statements will be TRUE?

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📖 Explanation

$W_{B}$ doubled (increased) $\rightarrow$ early effect is still present but its effect less severe relative to previous $W_{B}$ . Slope $I_{C}$ versus $V_{C E}$ decreases.

Q29GATE 2015NAT

An npn BJT having reverse saturation current $I_{S} = 10^{-15}$ A is biased in the forward active region with $V_{BE}$ = 700 mV. The thermal voltage ( $V_{T}$ ) is 25 mV and the current gain ( $\beta$ ) may vary from 50 to 150 due to manufacturing variations. The maximum emitter current (in $\mu$ A) is ________.

🚀 Solve in Practice Mode

📖 Explanation

\begin{aligned} I_{C} &=I_{s} e^{V_{B E} / V_{T}} \\ I_{E} &=\frac{\beta+1}{\beta} I_{C} \\ &=\frac{\beta+1}{\beta} I_{S} \cdot e^{V_{B E} / V_{T}} \end{aligned}

$I_{E}$ will be maximum when $\beta$ is 50.

\begin{aligned} &=(1.02)\left(10^{-9} \times 10^{-6}\right) e^{\frac{700 \times 10^{-3}}{25 \times 10^{-3}}} \\ &=1475 \mu \mathrm{A} \end{aligned}

Q30GATE 2015NAT

A MOSFET in saturation has a drain current of 1 mA for $V_{DS} = 0.5$ V. If the channel length modulation coefficient is 0.05 $V^{-1}$ , the output resistance (in $k\Omega$ ) of the MOSFET is _________.

🚀 Solve in Practice Mode

📖 Explanation

Under channel length modulation,

\begin{aligned} I_{D}&=I_{\text {Dsat }}\left(1+\lambda V_{\text {DS }}\right)\\ \frac{d I_{D}}{d V_{D S}} &=\frac{1}{r_{0}}=\lambda I_{\text {Dsat }} \\ r_{O} &=\frac{1}{\lambda I_{D \text { sat }}}=\frac{1}{0.05 \times 10^{-3}}=20 \mathrm{k} \Omega \end{aligned}

Q31GATE 2014NAT

The slope of the $I_{D}$ vs. $V_{GS}$ curve of an n-channel MOSFET in linear regime is $10^{-3}\Omega ^{-1}$ at $V_{DS}$ = 0.1V. For the same device, neglecting channel length modulation, the slope of the $\sqrt{I_{D}}$ vs. $V_{GS}$ curve (in $\sqrt{A}/V$ ) under saturation regime is approximately_____.

🚀 Solve in Practice Mode

📖 Explanation

We known that for linear region,

\begin{aligned} I_{D} &=K_{n}\left[\left(V_{G S}-V_{t}\right) V_{D S}-\frac{V_{D S}^{2}}{2}\right]\$ \\ \frac{\partial I_{D}}{\partial V_{G S}} &=K_{n} V_{D S}\\ \frac{10^{-3}}{0.1}&=K_{n} \\ \text{i.e.} \quad K_{n}&=10^{-2} \\ \end{aligned}

and for saturation region

\begin{aligned} I_{D} &=\frac{K_{n}}{2}\left(V_{G S}-V_{t}\right)^{2} \\ \sqrt{I_{D}} &=\sqrt{\frac{K_{n}}{2}}\left(V_{G S}-V_{t}\right) \\ \frac{\partial \sqrt{I_{D}}}{\partial V_{G S}} &=\sqrt{\frac{K_{n}}{2}}\\ \text{So }\quad\frac{\partial \sqrt{I_{D}}}{\partial V_{G S}}&=\sqrt{\frac{10^{-2}}{2}}=0.0707 \frac{\sqrt{A}}{V} \end{aligned}

Q32GATE 2014NAT

Consider two BJTs biased at the same collector current with area $A_{1}=0.2\mu m \times 0.2\mu m$ and $A_{2}=300 \mu m \times 300 \mu m$ . Assuming that all other device parameters are identical, kT/q = 26 mV, the intrinsic carrier concentration is $1 \times 10^{10}cm^{-3},$ and $q=1.6 \times 10^{-19}C$ , the difference between the base-emitter voltages (in mV) of the two BJTs (i.e., $V_{BE1}-V_{BE2}$ ) is _____.

🚀 Solve in Practice Mode

📖 Explanation

$I_{C}$ is given by

\begin{aligned} I_{C} &=I_{S} \exp \left[\frac{V_{B E}}{\eta V_{T}}\right] \\ I_{G} &=I_{S_{1}} \exp \left[\frac{V_{B E_{1}}}{\eta V_{T}}\right] &\ldots(i)\\ I_{C_{2}} &=I_{S_{2}} \exp \left[\frac{V_{B E_{2}}}{\eta V_{T}}\right]&\ldots(ii) \end{aligned}

According to given condition,

\begin{aligned} I_{G}&= I_{C_{2}} \\ I_{S_{1}} \exp \left[\frac{V_{B E_{1}}}{\eta V_{T}}\right]&=I_{S_{2}} \exp \left[\frac{V_{B E_{2}}}{\eta V_{T}}\right] \\ V_{B E_{1}}-V_{B E_{2}} &=\eta V_{T} \ln \left[\frac{I_{S_{2}}}{I_{S_{1}}}\right] \\ V_{B E_{1}}-V_{B E_{2}} &=26 \ln \left[\frac{300 \times 300}{0.2 \times 0.2}\right]\\ \because \quad\eta&=2 for Si BJT\\ V_{B E_{1}}-V_{B E_{2}}&=380 .28 \mathrm{mV} \end{aligned}

Q33GATE 2014NAT

A BJT is biased in forward active mode. Assume $V_{BE}$ = 0.7 V, kT/q = 25mV and reverse saturation current $I_{S}=10^{-13} A$ . The transconductance of the BJT (in mA/V) is _____.

🚀 Solve in Practice Mode

📖 Explanation

We know that,

\begin{aligned} g_{m} &=\frac{I_{c}}{V_{T}} \\ \text{where}\quad I_{c} &=I_{s} e^{\frac{V_{B E}}{V_{T}}}\\ \text { So, } I_{c}&=10^{-13} \times e^{\frac{0.7}{0.025}} \\ I_{c}&=0.144 \mathrm{mA}\\ \text { Hence, }\quad g_{m}&=\frac{0.144}{0.025}=5.76 \mathrm{mAN} \end{aligned}

Q34GATE 2014NAT

An ideal MOS capacitor has boron doping-concentration of $10^{15} cm ^{-3}$ in the substrate. When a gate voltage is applied, a depletion region of width 0.5 $\mu$ m is formed with a surface (channel) potential of 0.2 V. Given them is formed with a surface (channel) potential of 0.2 V. Given the $\varepsilon _{0}=8.854 \times 10^{-14}F/cm$ and the relative permittivities of silicon and silicon dioxide are 12 and 4, respectively, the peak electric field (in V/ $\mu$ m) in the oxide region is _____.

🚀 Solve in Practice Mode

📖 Explanation

Peak electric field in the oxide region is

\begin{aligned} E_{o x} &=\frac{E_{s}}{\epsilon_{o x}} E_{s} \\ \text{and}\quad E_{s} &=\frac{0.2 \times 2}{0.5}\\ E_{s}&=0.8 \mathrm{V} / \mu \mathrm{m}\\ \therefore \quad E_{o x} &=\frac{12}{4} \times 0.8 \\ E_{o x} &=2.4 \mathrm{V} / \mu \mathrm{m} \end{aligned}

Q35GATE 2014NAT

A depletion type N-channel MOSFET is biased in its linear region for use as a voltage controlled resistor. Assume threshold voltage $V_{TH}=-0.5 V,V_{GS}=2.0 V$ , $V_{DS}=5 V, W/L=100$ , $C_{OX}=10^{-8} F/cm^{2}$ and $\mu _{n}=800 cm^{2}/V-s$ . The value of the resistance of the voltage controlled resistor (in $\Omega$ ) is ______.

🚀 Solve in Practice Mode

📖 Explanation

Voltage controlled resistance $r_{D S}$ is is given by

\begin{aligned} r_{D S} &=\frac{1}{\left(\mu_{n} C_{o x}\right)\left(\frac{W}{L}\right)\left(V_{G S}-V_{t}\right)} \\ r_{D S} &=\frac{1}{800 \times 10^{-8} \times 100 \times (2+0.5)} \\ r_{D S} &=500 \Omega \end{aligned}

Q36GATE 2012MCQ

The source of a silicon ( $n_{i} = 10^{10}$ per $cm^{3}$ ) n-channel MOS transistor has an area of 1 sq $\mu$ m and a depth of 1 $\mu$ m. If the dopant density in the source is $10^{19}/cm^{3}$ , the number of holes in the source region with the above volume is approximately

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📖 Explanation

\begin{aligned} n_{i} &=10^{10} / \mathrm{cm}^{3} \\ A &=1 \times 10^{-12} \mathrm{m}^{2} \\ d &=10^{-6} \mathrm{m} \\ V &=A d=10^{-18} \mathrm{m}^{3} \\ &=10^{-12} \mathrm{cm}^{3} \\ N_{D} &=n=10^{19} / \mathrm{cm}^{3} \\ p &=\frac{n_{i}^{2}}{N_{D}}=\frac{10^{20}}{10^{19}}=10 / \mathrm{cm}^{3} \end{aligned}

So, holes in volume V is $H=p V=10^{-11}$ since, holes number can not be a decimal number so H=0

Q37GATE 2012MCQ

In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta$ =20nm. The transistor is of width 1 $\mu$ m. The depletion width formed at every p-n junction is 10 nm. The relative permittivities of Si and $SiO_{2}$ , respectively, are 11.7 and 3.9, and $\varepsilon _{0}=8.9\times 10^{-12}$ F/m. The source-body junction capacitance is approximately

🚀 Solve in Practice Mode

📖 Explanation

Source body junction capacitor,

\begin{aligned} C_{j}&=\frac{\in A}{d}=\frac{\epsilon_{0} \in_{T} A}{d}\\ \text{here, }\quad \epsilon_{r}&=11.7 \text{ as there is Si only y }\\ A&=1 \mu \mathrm{m} \times 0.2 \mu \mathrm{m}=0.2 \times 10^{-12} \mathrm{m}^{2}\\ d&= \text{depletion width of p-n junction}\\ d&=10 \mathrm{nm}=10^{-8} \mathrm{m} \\ \text{So,}\quad C_{j}&=\frac{8.9 \times 10^{-12} \times 11.7 \times 0.2 \times 10^{-12}}{10^{-8}}\\ C_{j}&=2.082 \times 10^{-15} \mathrm{F} \\ C_{j} &\cong 2 \mathrm{pF} \end{aligned}

Q38GATE 2011MCQ

The channel resistance of an N-channel JFET shown in the figure below is 600 $\Omega$ when the full channel thickness ( $t_{ch}$ ) of 10 $\mu m$ is available for conduction. The built-in voltage of the gate $P^+ N$ junction ( $V_{bi}$ ) is -1 V. When the gate to source voltage ( $V_{GS}$ ) is 0 V, the channel is depleted by 1 $\mu m$ on each side due to the builtin voltage and hence the thickness available for conduction is only 8 $\mu m$ . The channel resistance when $V_{GS}$ =0 V is

🚀 Solve in Practice Mode

📖 Explanation

Depletion layer width

\begin{aligned} w &\propto \sqrt{V_{G S}+V_{b i}}\\ \text { Given, } & V_{b i}=-1 \\ \text { and for, } & V_{G S}=0 \mathrm{V}, w_{1}=1 \mu \mathrm{m}\\ \text{Now for, }\quad V_{G S}&=-3 \mathrm{V}, w_{2} \text{ can be calculated}\\ \text{as }\quad \frac{w_{1}}{w_{2}}&=\sqrt{\frac{0-1}{-3-1}}=\frac{1}{2} \\ \Rightarrow \quad w_{2}&=2 \mu m \\ \end{aligned}

Channel width $\uparrow \Rightarrow$ channel resistance $\uparrow$ For $10 \mu \mathrm{m}$ channel resistance $=600 \Omega$ For $8 \mu \mathrm{m}$ channel resistance $=\frac{600 \times 100}{8}=750 \Omega$

Q39GATE 2011MCQ

For a BJT the common base current gain $\alpha$ = 0.98 and the collector base junction reverse bias saturation current $I_{CO} = 0.6 \mu A$ . This BJT is connected in the common emitter mode and operated in the active region with a base drive current $I_{B}= 20 \mu A$ . The collector current $I_{C}$ for this mode of operation is

🚀 Solve in Practice Mode

📖 Explanation

\begin{aligned} I_{C} &=\beta I_{B}+(1+\beta) I_{C O} \\ \beta &=\frac{\alpha}{1-\alpha}=\frac{0.98}{1-0.98}=49 \\ I_{C}&=49 \times 20+50 \times 0.6 \\ \therefore \quad &=980+30=1010 \mu \mathrm{A} \\ \text{or}\quad I_{C}&=1.01 \mathrm{mA} \end{aligned}

Q40GATE 2010MCQ

At room temperature, a possible value for the mobility of electrons in the inversion layer of a silicon n-channel MOSFET is

🚀 Solve in Practice Mode

📖 Explanation

Currently no explanation available

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