Memory Management Practice Questions

The number of TLB entries is calculated by dividing the TLB reach by the page size: $2^{20} \text{ B} / 2^{12} \text{ B} = 2^8 = 256$ entries.
The bits required for the page number are $\log_2(64 \text{ GB} / 4 \text{ KB}) = \log_2(2^{36} / 2^{12}) = 24$ bits.
The bits required for the frame number are $\log_2(1 \text{ GB} / 4 \text{ KB}) = \log_2(2^{30} / 2^{12}) = 18$ bits.
The total size per entry is $4 \text{ (PID)} + 24 \text{ (Page No)} + 18 \text{ (Frame No)} + 2 \text{ (Control)} = 48 \text{ bits}$, which equals $6 \text{ bytes}$.
The total size of the TLB is $256 \times 6 \text{ bytes} = 1536 \text{ bytes}$.

[CORRECT_OPTION: N/A]

This question tests your understanding of the relationship between the TLB, Page Table, and Cache. The key components and rules are:

• TLB: A cache for the Page Table. It stores recent virtual-to-physical address translations.
• Page Table: Resides in main memory and holds all virtual-to-physical address mappings. A "page table miss" means the page is not in main memory (a page fault).
• Cache: A hardware cache that uses physical addresses.
• System Rule: If a page is removed from main memory, all its corresponding blocks in the cache are invalidated.

Let's analyze the event sequences:

Sequence B: TLB hit, Page table miss, Cache hit
A TLB hit means a valid translation for the virtual page exists in the TLB. Since the TLB is a cache for the Page Table, this implies the corresponding entry must also be valid in the Page Table. A "Page table miss" indicates the page is not in main memory. A valid translation cannot exist in the TLB (TLB hit) for a page that is simultaneously not present in the main memory (Page table miss). This is a fundamental contradiction.

Sequence C: TLB miss, Page table miss, Cache hit
A "Page table miss" signifies that the required page is not present in main memory, which results in a page fault. According to the system rule, if a page is not in memory, its corresponding cache blocks must be marked invalid. Therefore, it is impossible to have a Cache hit for a page that has caused a Page table miss.

Sequence A: TLB miss, Page table hit, Cache hit
This sequence is possible. The TLB doesn't have the translation (miss), but the Page Table does (hit). The MMU gets the physical address from the Page Table and then finds the data at that address in the cache (hit).

Sequence D: TLB miss, Page table miss, Cache miss
This sequence is also possible. The translation is not in the TLB (miss) and the page is not in main memory (page table miss), resulting in a page fault. Since the page isn't in memory, its data is correctly not found in the cache (miss).

Logical address space = $2^{32}$ bytes. This implies a logical address of 32 bits.
Page size = 4096 bytes = $2^{12}$ bytes.
The offset within the desired page (page offset) is 12 bits.
The system uses two-level hierarchical paging. A logical address is structured as:
[Outer Page Table Index] [Inner Page Table Offset] [Page Offset]
Let's denote the components as $P_1$ (outer index), $P_2$ (inner offset), and $D$ (page offset).
So, $P_1$ is the $b$-bit index to the outer page table.
$D = 12$ bits.
The size of each inner page table entry is 8 bytes.
The number of entries in an inner page table is Page Size / Entry Size = $4096 / 8 = 2^{12} / 2^3 = 2^9$.
Thus, the Inner Page Table Offset ($P_2$) requires 9 bits.
The total logical address is 32 bits.
$b + P_2 + D = 32$ bits.
$b + 9 + 12 = 32$.
$b + 21 = 32$.
$b = 32 - 21 = 11$ bits.
The value of $b$ is 11.

The question asks to identify the page replacement policy given the initial and final states of three frames for a specific page reference string.
The page reference string is $1, 2, 3, 4, 5, 4, 1, 6, 4, 5, 1, 3, 2$. The frames have a capacity of three pages.
We apply the Optimal page replacement policy, which works by replacing the page that will not be used for the longest period of time in the future.
By simulating the Optimal policy, we get the following sequence of frames:

• Initially: Empty
• After 1, 2, 3: {1, 2, 3} (faults for 1, 2, 3)
• After 4: Page 1 is replaced by 4 (fault) as 1 is not used for longest duration. Frames: {4, 2, 3}
• After 5: Page 2 is replaced by 5 (fault) as 2 is not used for longest duration. Frames: {4, 5, 3}
• After 4, 1, 6, 4, 5, 1: The frames evolve as shown in the solution, matching the given 'after' state.
  The final state matches the result of the Optimal page replacement policy, is correct.

To determine the maximum number of entries in the page table, we first need to find the number of bits used for the page number in the logical address.

Given:

1. Logical Address Size = 32 bits
2. Page Size = 2048 bytes

First, convert the page size to a power of 2:
$2048 \text{ bytes} = 2^{11} \text{ bytes}$
The number of bits for the page offset (or displacement) is equal to the exponent of 2 in the page size.
So, Page Offset bits = 11 bits.

The logical address is divided into two parts: Page Number and Page Offset.
$\text{Logical Address Size} = \text{Page Number bits} + \text{Page Offset bits}$
$32 \text{ bits} = \text{Page Number bits} + 11 \text{ bits}$
Therefore, Page Number bits = $32 - 11 = 21$ bits.

The maximum number of entries in the page table is determined by the number of unique page numbers possible in the logical address space.
$\text{Maximum Number of Page Table Entries} = 2^{\text{Page Number bits}}$
$\text{Maximum Number of Page Table Entries} = 2^{21}$

To determine the number of page faults, we simulate the modified optimal page replacement algorithm with three initially empty frames. The OS predicts up to the next 4 page references.

Page references: 1, 3, 2, 4, 2, 3, 1, 2, 4, 3, 1, 4

1. Page 1: Frame empty. Fault. Frames: [1, _, _]
2. Page 3: Frame empty. Fault. Frames: [1, 3, _]
3. Page 2: Frame empty. Fault. Frames: [1, 3, 2]
4. Page 4: Frames full. Predict next 4 references: (4, 2, 3, 1). Page 1 is used last (at index 6), page 3 at index 5, page 2 at index 4. Replace 1 (used furthest in future). Fault. Frames: [4, 3, 2]
5. Page 2: Hit. Frames: [4, 3, 2]
6. Page 3: Hit. Frames: [4, 3, 2]
7. Page 1: Frames full. Predict next 4 references: (1, 2, 4, 3). Page 2 at index 7, page 4 at index 8, page 3 at index 9. Replace 4. Fault. Frames: [1, 3, 2]
8. Page 2: Hit. Frames: [1, 3, 2]
9. Page 4: Frames full. Predict next 4 references: (4, 3, 1, 4). Page 3 at index 9, page 1 at index 10, page 2 is not in prediction (used furthest). Replace 2. Fault. Frames: [1, 3, 4]
10. Page 3: Hit. Frames: [1, 3, 4]
11. Page 1: Hit. Frames: [1, 3, 4]
12. Page 4: Hit. Frames: [1, 3, 4]

Total page faults: 6

[CORRECT_OPTION: N/A]

Each inner page table (IPT) can hold $\frac{4 \text{ KB}}{4 \text{ bytes}} = 1024$ entries. The outer page directory (OPD) is always allocated, taking $1$ page.

1. Minimum pages ($X$): To minimize the number of IPTs, we pack the $2000$ unique page accesses into as few IPTs as possible. Since each IPT holds $1024$ entries, we need $\lceil 2000/1024 \rceil = 2$ IPTs. Thus, $X = 1 \text{ (OPD)} + 2 \text{ (IPTs)} = 3$.

2. Maximum pages ($Y$): To maximize the number of IPTs, we distribute the $2000$ entries to utilize the maximum number of available IPT slots in the OPD ($1024$ slots). By placing $1$ entry in each of the first $1023$ IPTs, we use $1023$ IPT pages, with the remaining $2000 - 1023 = 977$ entries placed in the $1024^{th}$ IPT. Thus, $Y = 1 \text{ (OPD)} + 1024 \text{ (IPTs)} = 1025$.

The value of $X + Y$ is:
$X + Y = 3 + 1025 = 1028$

[CORRECT_OPTION: N/A]

The Memory Management Unit (MMU) is a hardware component responsible for managing the virtual memory system. Its primary responsibilities include:
(b) Translating virtual addresses to physical addresses: This is the core function of the MMU, performed using page tables.
(c) Raising a trap when a process tries to write to a page marked with read-only permission: The MMU enforces memory protection by checking permissions in the page table entries and generates a trap (page fault) if a violation occurs.
(d) Raising a trap when a virtual address is not found in the page table: If a virtual address does not have a corresponding entry in the page table (e.g., due to a non-resident page or an invalid address), the MMU generates a page fault trap.
(a) Allocating a new page table for a newly created process: This is a responsibility of the Operating System (OS), not the MMU hardware. The OS manages page tables, while the MMU uses them for translation and protection.
Therefore, (b), (c), and (d) are responsibilities of the MMU.

Given:
Page size = 2 KB
Virtual Address (VA) = 2500 (decimal)
Pages 0, 1, 2, 3 are stored in page frames 1, 3, 2, 0 respectively.

First, determine the page size in bytes and then in a power of 2:
Page size = $2 \text{ KB} = 2 \times 1024 \text{ bytes} = 2 \times 2^{10} \text{ bytes} = 2^{11} \text{ bytes}$.
This means the page offset requires 11 bits.

Next, find the virtual page number (VPN) and offset from the given virtual address (VA):
VA = 2500 (decimal)
Virtual Page Number (VPN) = $\lfloor \text{VA} / \text{Page Size} \rfloor = \lfloor 2500 / 2048 \rfloor = \lfloor 1.22 \rfloor = 1$.
Page Offset = $\text{VA} \pmod{\text{Page Size}} = 2500 \pmod{2048} = 452$.

The virtual page number is 1. We look up the page table to find its corresponding physical page frame number.
Given mapping:
Virtual Page 0 $\rightarrow$ Physical Page Frame 1
Virtual Page 1 $\rightarrow$ Physical Page Frame 3
Virtual Page 2 $\rightarrow$ Physical Page Frame 2
Virtual Page 3 $\rightarrow$ Physical Page Frame 0

For Virtual Page 1, the Physical Page Frame Number (PFN) is 3.

Now, construct the Physical Address (PA):
Physical Address = (Physical Page Frame Number $\times$ Page Size) + Page Offset
PA = $(3 \times 2048) + 452$
PA = $6144 + 452$
PA = $6596$ (decimal).

Let's also express this in binary, as the solution does.
PFN = 3 (decimal) = $011_2$.
Page offset = 452 (decimal). Convert 452 to 11-bit binary:
$452 = 256 + 128 + 64 + 4 = 2^8 + 2^7 + 2^6 + 2^2$.
So, 452 in 11-bit binary is $0011100100_2$.
Physical address in binary = PFN bits + Offset bits
PFN uses at least 2 bits to represent '3'. Offset uses 11 bits.
PA in binary = $011_2$ (PFN) concatenated with $0011100100_2$ (Offset).
Assuming the PFN block is 2 bits long (to represent 0-3), then the VA is 13 bits (2 for VPN + 11 for offset).
VPN = 1 ($01_2$). Offset = 452 ($0011100100_2$).
Physical Address = PFN (3, $011_2$) + Offset (452, $0011100100_2$).
The number of bits for PFN depends on the maximum number of frames. The problem uses page frames 0-3, so 2 bits for PFN.
PA in binary: PFN (3 as $11_2$) + Offset (452 as $0011100100_2$)
PA = $11 \text{ (PFN)} | 0011100100 \text{ (Offset)} = 110011100100_2$.
Convert this binary to decimal:
$110011100100_2 = 2^{11} + 2^{10} + 2^7 + 2^6 + 2^5 + 2^2 = 2048 + 1024 + 128 + 64 + 32 + 4 = 3300$.
This is not 6596.

Let's recheck the format of the physical address. Typically, PFN is concatenated with offset.
PFN = 3.
Offset = 452.
The solution says $(1100111000100)_2$. This is 13 bits.
The offset is 11 bits ($2^{11}$ bytes). The remaining bits are for PFN.
Let's see the given solution's binary value: $1100111000100_2$.
The last 11 bits are $0111000100_2$. This is $2^9 + 2^8 + 2^7 + 2^2 = 512+256+128+4 = 900$.
The first two bits are $11_2$, which is PFN=3.
So the offset in the solution's binary is $900$.
This does not match our calculated offset of 452. This suggests either our breakdown or the solution's binary representation has an issue with the problem's values.

Let's re-calculate $6596$ in binary to see if it matches the solution's binary string:
$6596 \div 2 = 3298 \text{ R } 0$
$3298 \div 2 = 1649 \text{ R } 0$
$1649 \div 2 = 824 \text{ R } 1$
$824 \div 2 = 412 \text{ R } 0$
$412 \div 2 = 206 \text{ R } 0$
$206 \div 2 = 103 \text{ R } 0$
$103 \div 2 = 51 \text{ R } 1$
$51 \div 2 = 25 \text{ R } 1$
$25 \div 2 = 12 \text{ R } 1$
$12 \div 2 = 6 \text{ R } 0$
$6 \div 2 = 3 \text{ R } 0$
$3 \div 2 = 1 \text{ R } 1$
$1 \div 2 = 0 \text{ R } 1$
So, $6596_{10} = 1100111000100_2$. This matches the binary given in the solution.
This implies that my calculation $2500 \pmod{2048} = 452$ is correct, and PFN is 3.
Then $3 \times 2048 + 452 = 6144 + 452 = 6596$.
The binary form provided by the solution matches the decimal answer 6596, which is derived correctly.
The process is: VA (2500) -> VPN (1) and Offset (452). VPN (1) maps to PFN (3). PA = PFN * PageSize + Offset = 3 * 2048 + 452 = 6596.

Given:
Virtual address size = 57 bits.
Page size = 4 KB = $2^{12}$ bytes.
Page table entry (PTE) size = 8 bytes = $2^3$ bytes.

First, calculate the number of bits for the page offset:
Page offset bits = $\log_2(\text{Page size}) = \log_2(4 \text{ KB}) = \log_2(2^{12}) = 12$ bits.

The remaining bits in the virtual address are for the virtual page number (VPN):
VPN bits = Virtual address size - Page offset bits = $57 - 12 = 45$ bits.

Each level of the page table maps a portion of the VPN. The number of entries in a page table that can fit into one page determines the number of bits mapped by each level.
Number of PTEs per page = Page size / PTE size = $2^{12} \text{ bytes} / 2^3 \text{ bytes} = 2^9$ entries.
Number of bits mapped by each level = $\log_2(\text{Number of PTEs per page}) = \log_2(2^9) = 9$ bits.

To find the number of levels ($L$), divide the total VPN bits by the bits mapped per level:
$L = \text{VPN bits} / \text{Bits per level} = 45 \text{ bits} / 9 \text{ bits/level} = 5$ levels.

Given:
Array $D[128][128]$ stored in row-major order.
Page frame size = 512 elements.
Number of physical page frames = 30.
Access pattern: for (int i = 0; i < 128; i++) for (int j = 0; j < 128; j++) D[j][i] *= 10;
This access pattern is column-major.

Since the array is stored in row-major order, accessing elements D[j][i] means that for a fixed i, D[0][i], D[1][i], ..., D[127][i] are accessed. These elements are far apart in memory.
Each row has 128 elements. A page holds 512 elements. So, 4 rows fit into one page ($512 / 128 = 4$).
When D[j][i] is accessed, it belongs to row j. Since the access is column-major, for a fixed i, we iterate through j.
When D[0][i] is accessed, it causes a page fault for the page containing row 0.
When D[1][i] is accessed, it causes a page fault for the page containing row 1.
...
When D[3][i] is accessed, it causes a page fault for the page containing row 3.
These 4 rows are in the same page. So, the first access to D[0][i] causes a page fault, and subsequent accesses to D[1][i], D[2][i], D[3][i] are page hits.
After D[3][i], D[4][i] is accessed. This is in a new page (containing rows 4-7), causing another page fault.
This means for each column i, we will incur a page fault for every 4 rows.
Number of rows = 128. Number of page faults per column = $128 / 4 = 32$.
Total number of columns = 128.
Total page faults = $32 \times 128 = 4096$.

The LRU policy and 30 physical page frames are relevant if the number of pages accessed exceeds the available frames, leading to page replacements.
Total pages in the array = $128 \text{ rows} / 4 \text{ rows/page} = 32 \text{ pages}$.
Since 32 pages are needed and only 30 frames are available, there will be page replacements.
However, the access pattern is sequential across columns. For each i, we access D[0][i] to D[127][i].
When i=0, we fault for pages 0, 1, ..., 31. Since only 30 frames are available, pages will be replaced.
When i=1, we again access D[0][1], which will likely cause a page fault if page 0 was replaced.
Since the access pattern is column-major and the storage is row-major, each access to a new row (for a fixed column) will likely cause a page fault, unless that row's page is still in memory.
Given 30 frames and 32 pages, if we access all 32 pages, 2 pages will be swapped out.
For each column, we access 32 distinct pages. Since we only have 30 frames, 2 pages will be evicted and reloaded.
So, for each column, we will have 32 page faults.
Total page faults = $128 \text{ columns} \times 32 \text{ page faults/column} = 4096$.

Let's analyze each statement regarding cache and TLB:
(A) "The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address." This statement is TRUE. TLBs (Translation Lookaside Buffers) are typically implemented as associative caches, allowing simultaneous comparison of the incoming virtual page number with all entries in the TLB to find a match quickly.
(B) "If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory." This statement is TRUE. A TLB hit means that the translation from virtual address to physical address was found, and the corresponding page is present in a physical frame in main memory. Even if the data itself is not in the CPU cache (cache miss), it must reside in main memory because its page address translation was successful.
(C) "The memory access time using a given inverted page table is always same for all incoming virtual addresses." This statement is FALSE. In an inverted page table, page numbers are searched by hashing the virtual page number. If a hash collision occurs, a linked list (or similar data structure) needs to be traversed, which takes variable time depending on the length of the collision chain. Therefore, access time is not always the same for all virtual addresses.
(D) "In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same." This statement is FALSE. If two distinct virtual addresses V1 and V2 map to the same hash value (a collision), then the page table lookup will involve traversing a chain of entries at that hash location. While the overall lookup time for different addresses might vary if one has a longer chain than the other, it's not guaranteed that these specific two addresses will have different memory access times. If they both end up at the same slot and are found at the beginning of their respective chains after the initial hash, their access times could be similar. However, the more crucial point of a hashed page table is that access time is not constant for all addresses due to potential collisions and varying chain lengths. The statement says "will not be the same," which implies they must be different. It's possible for them to take the same amount of time if they are both the first entries in a collision chain, for example. The variability comes from different chain lengths, not necessarily from these two colliding addresses always taking different times.

The question asks for the statement that is FALSE. Statement (C) is definitively false because of hash collisions. Statement (D) is also false as access times for colliding entries might be the same. The solution points to C.

The page fault rate is the ratio of page faults to total memory accesses. The total number of memory accesses is 15. We trace the page reference string using the Least Recently Used (LRU) policy with four frames to count the page faults (F) and hits (H).

The sequence of memory accesses and their outcomes is as follows:
7(F), 2(F), 7(H), 3(F), 2(H), 5(F), 3(H), 4(F), 6(F), 7(F), 7(H), 1(F), 5(F), 6(H), 1(H).

By counting the faults in the sequence above, we find there are a total of 9 page faults.

The page fault rate is calculated as:
$\text{Page Fault Rate} = \frac{\text{Total Page Faults}}{\text{Total Memory Accesses}} = \frac{9}{15}$
$\frac{9}{15} = \frac{3}{5} = 0.6$
The page fault rate is 0.6.

Paging incurs memory overheads because page tables, which map virtual pages to physical frames, must be stored in main memory. This storage requirement adds to the overall memory consumption.
Paging also helps solve the issue of external fragmentation. By dividing physical memory into fixed-size frames and allocating them to processes, paging ensures that all available memory units are of the same size, thus eliminating external fragmentation.

The virtual address is 39 bits. Page size is 4 KB ($2^{12}$ bytes), so the page offset is 12 bits.
The remaining 27 bits are for the page table. With 3 levels, each level uses 9 bits ($27/3 = 9$).
Page table entry size is 8 bytes.
The process uses 2 GB ($2^{31}$ bytes) of virtual memory.
Number of pages = $\frac{2^{31}}{2^{12}} = 2^{19}$.
Each page table contains $2^9$ entries.
Number of 3rd level page tables = $\frac{2^{19}}{2^9} = 2^{10}$.
Number of 2nd level page tables = $\frac{2^{10}}{2^9} = 2^1 = 2$.
Number of 1st level page tables = $\frac{2^1}{2^9} = 1$ (since it's the root).
Total page tables = $1 + 2 + 2^{10} = 1 + 2 + 1024 = 1027$.
Total memory for page tables = $1027 \times 2^9 \times 8$ bytes.
This calculation is incorrect in the PDF. The number of entries in a page table is $2^9$. The size of each page table is $2^9 \times 8$ bytes.
Total memory for page tables = $1027 \times (2^9 \times 8)$ bytes.
$1027 \times 512 \times 8 = 1027 \times 4096$ bytes.
$1027 \times 4$ KB = 4108 KB.

Scenario A: Page Fault occurs on 10% of ALL references (Current Text)

This is the "Worst Case" scenario.

• EMAT (No Fault) = 125 ns
• Service Time ($S$) = 6000 ns
• AMAT = $0.9 \times 125 + 0.1 \times 6000$ = 712.5 ns

Scenario B: Page Fault occurs on 10% of TLB MISSES only

• TLB Hit (95%): $0.95 \times (20 + 100) = 114 \text{ ns}$
• TLB Miss (5%):
  • 90% of misses stay in memory: $0.05 \times 0.9 \times (20 + 200) = 9.9 \text{ ns}$
  • 10% of misses go to disk: $0.05 \times 0.1 \times (20 + 200 + 6000) = 31.1 \text{ ns}$
• AMAT = $114 + 9.9 + 31.1$ = 155 ns

Conclusion & Fix

The stored answer range (154.5 to 155.5) in your dashboard perfectly matches Scenario B.

Action Item: To make your explanation match the stored answer, you should update the wording in the "Step 3" part of your explanation to clarify that the 10% fault rate applies only to the 5% of cases where the TLB misses.

Revised Step 3 for your snippet:
"Since the stored answer is ~155 ns, the 10% page fault rate applies only to TLB misses ($5\%$).
Total AMAT = $0.95 \times 120 + 0.05 \times [0.9 \times 220 + 0.1 \times (220 + 6000)] = \mathbf{155 \text{ ns}}$."

External fragmentation occurs in dynamic memory allocation when available free memory is broken into small, non-contiguous pieces, preventing the allocation of a single large process. Compaction is an operating system technique used to relocate processes in memory to consolidate all allocated memory blocks together. By shifting these segments, the scattered free memory holes are combined into a single, large contiguous block of memory. This effectively allows the system to satisfy memory requests that were previously impossible due to disconnected memory space. Consequently, compaction serves specifically as a mechanism to resolve external fragmentation.

Let's analyze the memory allocation strategies and the resulting hole sizes. When an allocation is made, the remaining portion of the memory hole becomes a new, smaller hole.

1. First Fit: Allocates memory from the first hole large enough to satisfy the request. The remaining hole size can be anything from very small to very large, depending on the hole found.
2. Best Fit: Allocates memory from the smallest hole that is large enough. This strategy aims to leave the smallest possible remaining hole, thus minimizing fragmentation.
3. Worst Fit: Allocates memory from the largest available hole. This strategy intends to leave a large remaining hole, hoping it will be useful for future large requests.

Comparing Best Fit and First Fit:
Best fit, by definition, chooses the smallest sufficient hole. This means the fragment left behind by best fit will always be less than or equal to the fragment left by first fit (if first fit happened to choose a larger initial hole). Therefore, the hole created by best fit is never larger than the hole created by first fit.

To find the minimum number of frames required to achieve the minimum number of page faults (which corresponds to the number of unique pages), we first identify the unique pages in the reference string: $\{1, 2, 3, 4, 5, 6, 7\}$. The number of unique pages is 7, meaning the minimum possible number of page faults is 7 (the compulsory faults).

Using the LRU (Least Recently Used) replacement strategy:

1. With $N=6$ frames, the sequence of references produces exactly 7 page faults:
   • Pages $\{1, 2, 3, 4, 5, 6\}$ are loaded sequentially (6 faults).
   • Subsequent references to $\{2, 1, 2, 3\}$ are hits.
   • The reference to $7$ causes 1 page fault (replacing 4), and the remaining references $\{6, 3, 2, 1, 2, 3, 6\}$ are all hits.
   • Total faults = $6 + 1 = 7$.
2. With $N < 6$ frames (e.g., $N=5$), the sequence causes more than 7 page faults because the working set cannot fit in the available frames, leading to additional replacement faults.

Therefore, the minimum number of frames required to limit the page faults to the compulsory 7 is 6.