Q81MediumNAT
A 4-bit binary ripple counter uses JK flip-flops with propagation delay of 20 ns per flip-flop. The maximum clock frequency for reliable operation is 12.5 MHz. What is the number of flip-flops in the counter?
GATE CSE · Digital Logic
Master topic for Sequential Circuit. Includes Flip-Flops, Counters & Registers.
116 questions · 0 PYQs · 20 AI practice · GATE CSE 2027
A 4-bit binary ripple counter uses JK flip-flops with propagation delay of 20 ns per flip-flop. The maximum clock frequency for reliable operation is 12.5 MHz. What is the number of flip-flops in the counter?
A decade counter (4-bit BCD counter) has outputs Q3 Q2 Q1 Q0. After reset, it counts from 0 to 9 and then resets. What is the frequency of Q3 output if the clock frequency is 10 kHz?
A 4-bit parallel-in parallel-out (PIPO) register is loaded with data D3 D2 D1 D0 = 1101. The register has asynchronous clear (active low) and clock. If the clear input is activated (set to 0) for one clock cycle while the clock is high, what is the output after the clock cycle? (Assume clear overrides clock).
A 4-bit ring counter is initialized to 1000. What is the state after 5 clock pulses?
A negative edge-triggered D flip-flop has setup time 5 ns, hold time 2 ns, and propagation delay 8 ns. The clock frequency is 100 MHz. What is the minimum time that the data must be stable before the clock edge?
In a 4-bit synchronous counter using JK flip-flops, the J and K inputs of the third flip-flop (counting from LSB) are:
Consider a positive edge-triggered JK flip-flop with active low preset and clear. Initially Q=0. The following sequence of inputs is applied: J=1, K=0, CLK=0; then CLK=1; then CLK=0; then CLK=1; then preset=0 (active low). The final output Q is:
The major drawback of an SR latch is:
A 4-bit synchronous counter has a clock of 100 MHz. The flip-flops have setup time 3 ns, hold time 2 ns, propagation delay 8 ns. The AND gates used have delay 4 ns. The maximum frequency (in MHz) is ______.
An 8-bit serial-in serial-out (SISO) shift register is initialized to 10101010. After 3 clock pulses, what is the content of the register? (Assume new input is 0 for each shift).
A 4-bit Johnson counter is initialized to 0000. What is the output after 9 clock pulses?
A positive edge-triggered D flip-flop has D = 1, clock = 0 initially. The clock then changes to 1 and back to 0. The output Q after the clock returns to 0 will be:
A 4-bit serial-in parallel-out (SIPO) shift register is initially empty. The serial input sequence is 1011 (applied LSB first). After 4 clock pulses, the parallel output is:
A positive edge-triggered D flip-flop has D = Q' (feedback). Initially Q=0. After 3 clock pulses, Q will be:
A 4-bit binary ripple counter is constructed using four flip-flops. If each flip-flop has a propagation delay of 25 ns, what is the maximum clock frequency (in MHz) at which the counter can operate reliably?
In a positive edge-triggered JK flip-flop, if J=1, K=1, and the clock is a square wave of 50% duty cycle, the output will:
A 3-bit synchronous counter using D flip-flops is designed to count in the sequence: 0, 2, 4, 6, 0, ... The D input expressions are:
A 4-bit ripple counter uses JK flip-flops with J=K=1. The propagation delay of each flip-flop is 25 ns. The maximum frequency at which the counter can count reliably is:
A 4-bit synchronous counter is constructed using T flip-flops. If the clock frequency is 10 MHz, what is the frequency of the output at the Most Significant Bit (MSB)?
For a positive edge-triggered T flip-flop, if T=1 and the initial output Q=0, after the clock pulse, the output will be:
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