Q101MediumMCQ
A processor spends 50% of its time waiting for memory due to cache misses. If memory bandwidth is doubled with no change in miss rate or latency, what is the maximum theoretical speedup for memory-bound applications?
GATE CSE · Computer Organization Architecture
Master topic for Pipeline Processor. Includes Pipelining, Performance & Parallelism.
110 questions · 0 PYQs · 10 AI practice · GATE CSE 2027
A processor spends 50% of its time waiting for memory due to cache misses. If memory bandwidth is doubled with no change in miss rate or latency, what is the maximum theoretical speedup for memory-bound applications?
In saving CPU state during an interrupt, what is stored and why?
In a pipelined datapath, which stage is typically responsible for calculating the branch target address?
Which of the following statements about pipeline hazards is/are CORRECT?
A 5-stage pipelined processor has stage delays of 180 ns, 250 ns, 150 ns, 170 ns, and 250 ns. The inter-stage latch delay is 10 ns. Assuming no stalls or hazards, the time to execute 1000 instructions is ______ microseconds (rounded to two decimal places).
In a shared memory multiprocessor, what coherence protocol uses a finite-state machine to monitor bus transactions and maintain cache consistency?
A 5-stage pipelined processor has stage delays: IF (5 ns), ID (7 ns), OF (10 ns), PO (8 ns), WO (6 ns), with buffer delay 1 ns. A program of 12 instructions is executed. I4 is a branch instruction taken to I9. Without branch prediction, the time to complete the program is ______ ns.
Which of the following best describes the advantage of vector processing over scalar pipelining?
A DMA module transfers characters to memory using cycle stealing from a device transmitting at 12800 bits per second. How many bytes will it transfer per second?
A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction. This unit is redesigned into a 5-stage pipeline operating at 2 GHz, with ideal throughput of 1 instruction per cycle. In program execution, 20% of instructions incur an average stall of 2 cycles due to data hazards, and another 20% incur an average stall of 3 cycles due to control hazards. The speedup achieved (rounded to one decimal place) is ______.
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