Q41MediumMSQ
In a demand paging system, which of the following events can occur during a page fault? (Select all that apply)
GATE CSE · Computer Organization Architecture
Practice problems for Memory Chip Design in Computer Organization & Architecture.
46 questions · 0 PYQs · 6 AI practice · GATE CSE 2027
In a demand paging system, which of the following events can occur during a page fault? (Select all that apply)
A computer has a 64-entry fully associative TLB. If the page size is 4 KB and the virtual address space is 32 bits, the number of bits in the TLB tag is __________ .
In a fully associative cache, the placement of a memory block into the cache is determined by:
In a RAID 4 system with 4 data disks and 1 parity disk, if each disk has a capacity of 100 GB, the total usable data capacity (in GB) is __________ .
In the memory hierarchy, which of the following correctly orders the memory types from fastest to slowest access time?
A cache uses a write-back policy with write-allocate. On a write miss, the processor writes to the cache and:
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