Memory Chip Design – GATE CSE Computer Organization ArchitecturePractice Questions & PYQs

Dynamic RAM (DRAM) stores each bit of data as an electrical charge within microscopic capacitors. Because these capacitors naturally lose their charge over time due to leakage currents, the stored information would eventually be lost if not periodically restored. To maintain data integrity, the system must perform a refresh cycle to read and rewrite the charge in every memory cell. The industry-standard interval for this operation is typically $2 \text{ ms}$. Consequently, the memory controller ensures the data is preserved by refreshing the memory array every $2 \text{ ms}$.

Paging can waste space within the last frame if the process size is not a multiple of page size (internal fragmentation). Segments vary in size, leading to external fragmentation. Segmented paging uses paging within segments, giving both the modular view of segmentation and easy allocation of paging. Inverted page tables have ONE entry per FRAME of physical memory, not per virtual page (D is false).

Direct mapping maps each block to exactly one line (A). Higher associativity reduces conflicts because more lines are available per set (B). In fully associative, every line's tag must be compared, requiring comparators equal to the number of lines (D). Tag bits actually DECREASE with higher associativity because fewer index bits are needed for the same cache size (C is false).

Block size = 64 bytes = 2^6 bytes. Therefore, the block offset requires log2(64) = 6 bits to identify a specific byte within the block.

Loop unrolling exploits temporal locality by reusing the same instructions and data within the loop body multiple times. Array sequential access exploits spatial locality because adjacent memory locations are accessed consecutively. Together, both types of locality are exploited.

In low-order interleaving with 4 modules, consecutive addresses map to different modules. The first word takes the full memory cycle of 100 ns. Each subsequent word is transferred from the next module after every bus cycle of 25 ns. With 8 words: word 0 at 100 ns, word 1 at 125 ns, word 2 at 150 ns, word 3 at 175 ns, word 4 at 200 ns, word 5 at 225 ns, word 6 at 250 ns, word 7 at 275 ns. Total time = 100 + (8-1) × 25 = 275 ns.

Belady's anomaly is the counter-intuitive phenomenon where increasing the number of page frames results in more page faults. FIFO is the only common algorithm among the options that suffers from this anomaly. Stack-based algorithms like LRU and Optimal never exhibit Belady's anomaly.

In N-way set-associative mapping, main memory is divided into sets and each set contains N cache lines (ways). A memory block maps to exactly one set (determined by index bits), but can be placed in any of the N lines within that set. With 4-way associativity and set 7, placement is restricted to any of the 4 lines in set 7.

TLB is a small, fast cache that stores recently used virtual-to-physical page table entries. It reduces the penalty of address translation by avoiding a full page table lookup in main memory for hits. On a TLB miss, the page table (or page table walker in hardware) is consulted.

DRAM uses address multiplexing where the same address pins carry first the row address (with RAS) and then the column address (with CAS). This halves the number of address pins required compared to providing all address bits simultaneously. For an n-bit address, only n/2 pins are needed.

Cache size = Number of sets × Associativity × Block size = 1024 × 4 × 16 bytes = 65536 bytes = 64 KB.

Block size = 32 bytes = 2^5, so block offset = 5 bits. Number of lines = 512 = 2^9, so index = 9 bits. Tag bits = 32 - (index + offset) = 32 - (9 + 5) = 32 - 14 = 18 bits.

Increasing associativity reduces conflict misses (B). Better replacement policies exploit locality better (C). Larger cache size reduces capacity misses (D). Increasing block size while keeping total cache size constant REDUCES the number of blocks in the cache, which may actually INCREASE conflict misses for certain access patterns, though it can improve spatial locality. This is not a guaranteed miss rate reduction.

SRAM uses 6 transistors per cell (flip-flop), is faster, more expensive, and does NOT require refreshing (B is false). DRAM uses 1 transistor + 1 capacitor per cell, is slower, cheaper, and requires periodic refresh. SRAM is used for cache; DRAM for main memory.

RAID 1 maintains an exact mirror (copy) of data on two or more disks. With 2 disks of capacity C each, total physical capacity is 2C, but since every block is duplicated, the usable capacity is only C. This provides fault tolerance at the cost of 50% storage efficiency.

High-order interleaving uses the high-order address bits to select the module, so consecutive addresses map to the SAME module (A). Low-order interleaving uses low-order bits, so consecutive addresses map to DIFFERENT modules (B), enabling parallel access and higher bandwidth for sequential patterns (C). High-order interleaving is indeed referred to as memory banking (D).

In MESI: Modified = present only in this cache, dirty, must be written back; Exclusive = present only in this cache, clean (matches memory), no other cache has it; Shared = present in multiple caches, clean; Invalid = not present in this cache. Exclusive allows a write to occur without bus transaction (silent upgrade to Modified).

Write-through updates both cache and memory, so memory always has latest data (A). Write-back only writes to memory on replacement, reducing bandwidth (B). Write-allocate fetches the block on write miss (C). No-write-allocate is typically paired with WRITE-THROUGH (not write-back), because with write-back, you'd need the block in cache to batch updates (D is false).

Block size = 16 bytes = 2^4, so block offset = 4 bits. Number of sets = Total lines / Associativity = 256 / 2 = 128 sets = 2^7, so set index = 7 bits. Tag bits = Total address bits - (set index + block offset) = 24 - (7 + 4) = 13 bits.

Effective Access Time = (Hit Rate × Cache Time) + (Miss Rate × Main Memory Time) = (0.9 × 10) + (0.1 × 100) = 9 + 10 = 19.0 ns.