Q21GATE 2016NAT

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is _______ .

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📖 Explanation

The total instruction word size is 32 bits.
To represent 40 distinct instructions, the opcode field requires $\lceil \log_2 40 \rceil = 6$ bits, since $2^5 < 40 < 2^6$ .
To address one of 24 general-purpose registers, each register operand field requires $\lceil \log_2 24 \rceil = 5$ bits, since $2^4 < 24 < 2^5$ .
Since there are two register operands, they consume a total of $2 \times 5 = 10$ bits.
The total bits used by the opcode and register fields are $6 + 10 = 16$ bits.
The remaining bits available for the immediate operand are $32 - 16 = 16$ bits.

Q23GATE 2015MCQ

The contents of the flag register after execution of the following program by 8085 microprocessor will be Program SUB A MVI B,(01)H DCR B HLT

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Q24GATE 2015MCQ

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location $(0100)_{16}$ and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is $(016E)_{16}$ . The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows: Store the current value of PC in the stack Store the value of PSW register in the stack Load the starting address of the subroutine in PC The content of PC just before the fetch of a CALL instruction is $(5FA0)_{16}$ . After execution of the CALL instruction, the value of the stack pointer is

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📖 Explanation

The CALL instruction performs two push operations onto the stack before transferring control. The stack grows upward, meaning the stack pointer (SP) increases with each push.

Initial SP value is $(016E)_{16}$ .
The first operation is to store the current Program Counter (PC) on the stack. Since the PC is 2 bytes, this increments the SP by 2. New SP = $(016E)_{16} + 2 = (0170)_{16}$ .
The second operation is to store the Program Status Word (PSW) on the stack. The PSW is also 2 bytes, so the SP is incremented by 2 again. New SP = $(0170)_{16} + 2 = (0172)_{16}$ .
The final operation, loading the subroutine address into the PC, does not affect the stack pointer.

Q25GATE 2014MCQ

Assume that 16-bit CPU is trying to access a double word stating at an odd address. How many memory operations are required to access the data?

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Q26GATE 2014NAT

Consider two processors P1 and P2 executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P2 takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P1. If the clock frequency of P1 is 1GHz, then the clock frequency of P2 (in GHz) is _________.

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📖 Explanation

Let $T_1$ and $T_2$ be the execution times for processors P1 and P2, respectively.
Let $F_1$ and $F_2$ be the clock frequencies, and $CPI_1$ and $CPI_2$ be the clock cycles per instruction.
Given $F_1 = 1 \, \text{GHz}$ . We know that execution time $T = \text{Instruction Count} \times \text{CPI} / \text{Frequency}$ .
Let the Instruction Count (IC) be the same for both processors.
$T_2 = T_1 - 0.25 T_1 = 0.75 T_1$
$CPI_2 = CPI_1 + 0.20 CPI_1 = 1.20 CPI_1$
Substituting these into the execution time formula:
$IC \times CPI_2 / F_2 = 0.75 \times (IC \times CPI_1 / F_1)$
$1.20 \times CPI_1 / F_2 = 0.75 \times CPI_1 / F_1$
$F_2 = (1.20 / 0.75) \times F_1 = (1.20 / 0.75) \times 1 \, \text{GHz} = 1.6 \, \text{GHz}$ .

[CORRECT_OPTION: 1.6]

Q27GATE 2014NAT

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________.

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📖 Explanation

The instruction format is 1-word long, which means 32 bits.
To support 45 instructions, the opcode field requires $\lceil \log_2 45 \rceil = 6$ bits.
There are 64 registers, so each register operand requires $\lceil \log_2 64 \rceil = 6$ bits. Since there are two register operands, they use $6 \times 2 = 12$ bits.
The total bits used by the opcode and register operands are $6 + 12 = 18$ bits.
The remaining bits for the immediate operand are $32 - 18 = 14$ bits.
For an unsigned integer, the maximum value representable with 14 bits is $2^{14} - 1 = 16384 - 1 = 16383$ .

The final answer is $\boxed{16383}$ .

Q28GATE 2013MCQ

Consider the following sequence of micro-operations. MBR $\leftarrow$ PC MAR $\leftarrow$ X PC $\leftarrow$ Y Memory $\leftarrow$ MBR Which one of the following is a possible operation performed by this sequence?

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📖 Explanation

The sequence of micro-operations indicates the following actions:

MBR $\leftarrow$ PC: The current value of the Program Counter (PC), which holds the address of the next instruction, is moved to the Memory Buffer Register (MBR). This effectively saves the return address.
MAR $\leftarrow$ X: An address X (likely the starting address of a service routine) is moved to the Memory Address Register (MAR).
PC $\leftarrow$ Y: The Program Counter is updated with a new address Y, which typically points to the beginning of a new routine.
Memory $\leftarrow$ MBR: The content of the MBR (the saved PC value) is written to memory at the address specified by MAR. This stores the return address on the stack or a dedicated memory location.

This entire sequence is characteristic of an interrupt service routine initiation, where the current program's execution context (PC) is saved, and control is transferred to a new routine (PC $\leftarrow$ Y).

The final answer is $\boxed{D}$

Q29GATE 2013MCQ

In 8086, the jump condition for the instruction JNBE is?

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Q30GATE 2013MCQ

How many number of times the instruction sequence below will loop before coming out of the loop? MOV AL, 00H A1: INC AL JNZ A1

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Q31GATE 2011MCQ

Find the memory address of the next instruction executed by the microprocessor (8086), when operated in real mode for CS=1000 and IP=E000

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Q32GATE 2009MCQ

A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be

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Q33GATE 2009MCQ

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for: I. Function locals and parameters II. Register saves and restores III. Instruction fetches

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Q34GATE 2009MCQ

Compared to CISC processors,RISC processors contain

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Q35GATE 2008MCQ

A processor that has the carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:

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Q36GATE 2008MCQ

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

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Q37GATE 2008MCQ

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for I. Function locals and parameters II. Register saves and restores III. Instruction fetches

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Q38GATE 2008MCQ

The Memory Address Register

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Q39GATE 2008MCQ

Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = -(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)- is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination $\longleftarrow$ source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

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Q40GATE 2008MCQ

Consider the following Assembly language program MVIA 30 H ACI 30 H XRA A POP H After the execution of the above program, the contents of the accumulator will be

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