Which of the following architecture is/are not suitable for realising SIMD?
GATE CSE · Computer Organization Architecture
Master topic for Machine Instruction. Includes Instruction Set Architecture (ISA), Basic Computer Organization.
113 questions · 20 PYQs · 0 AI practice · GATE CSE 2027
Which of the following architecture is/are not suitable for realising SIMD?
Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? I. It must be a trap instruction II. It must be a privileged instruction III. An exception cannot be allowed to occur during execution of an RFE instruction
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

Following table indicates the latencies of operations between the instruction producing the result and instruction using the result.
Consider the following code segment: Load R1, Loc 1; Load R1 from memory location Loc1 Load R2, Loc 2; Load R2 from memory location Loc 2 Add R1, R2, R1; Add R1 and R2 and save result in R1 Dec R2; Decrement R2 Dec R1; Decrement R1 Mpy R1, R2, R3; Multiply R1 and R2 and save result in R3 Store R3, Loc 3; Store R3 in memory location Loc 3 What is the number of cycles needed to execute the above code segment assuming each instruction takes one cycle to execute?
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction "INC R3", what return address will be pushed on to the stack?

Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction "bbs reg, pos, labbel" jumps to label if bit in position pos of register operand reg is one. a register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented. temp reg & mask Branch to label if temp is non-zero The variable temp is a temporary register. For correct emulation the variable mask must be generated by
Consider these two functions and two statements S1 and S2 about them. S1 : The transformation from work 1 to work 2 is valid, i.e., for any program state and input arguments, work 2 will compute the same output and have the same effect on program state as work 1 S2 : All the transformations applied to work 1 to get work 2 will always improve the performance (i.e. reduce CPU time) of work 2 compared to work 1

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?
The memory locations 1000,1001 and 1020 have data values 18,1 and 16 respectively before the following program is executed.
Which of the statements below is TRUE after the program is executed ?
If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations R1 M[100] M[100] R2 M[100] R3 can be replaced by
Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3. Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3. Let the clock cycles required fro various operations be as follows: Register to/from memory transfer : 3 clock cycles ADD with both operands in register : 1 clock cycle Instruction fetch and decode : 2 clock cycles per word The total number of clock cycles required to execute the program is

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments. Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its initial value?

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments. If the initial value of register A is A0 the value of register B after the program execution will be

What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after executing the following 8085 program ? MIV H, 5DH MIV L, 6BH MOV A, H ADD L
In 8085 which of the following modifies the program counter ?
Suppose a processor does not have any stack pointer register. Which of the following statements is true ?
To put the 8085 microprocessor in the wait state
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically: a) has fewer instructions b) has fewer addressing modes c) has more registers d) is easier to implement using hardwired control logic
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