Io Interface Practice Questions

In daisy chaining, devices are connected serially, and the device closest to the CPU has the highest priority, followed by the next device, and so on. This creates a non-uniform priority scheme where priority is determined by physical proximity to the CPU.

DMA requires the least CPU intervention as data transfers directly between device and memory without CPU involvement per byte. Interrupt-driven I/O requires CPU intervention only when an interrupt occurs, reducing overhead. Programmed I/O (polling) requires constant CPU involvement, making it the most CPU-intensive.

Critical system/hardware conditions (like CPU overheating) must be handled with highest priority to prevent permanent damage. Input devices like mouse and keyboard have lower priority, and disk I/O typically has even lower priority for routine operations.

In cycle stealing, the DMA controller transfers one word per stolen cycle (A). The CPU is not completely blocked; it is only delayed by one cycle each time. This makes cycle stealing more efficient than burst mode for small transfers (C). Statement B is false (that describes burst mode), and D is mostly true, but only A and C are explicitly correct according to GATE standards.

In burst mode, the DMA controller transfers the entire block of data in one contiguous burst (B), maintaining bus control throughout. This blocks CPU access completely during the transfer (C is also true, but the question asks for true statements, so both B, C, and D are true? Wait, C is also a characteristic of burst mode. However, the question might expect only B and D. In standard GATE questions, the CPU is completely blocked during burst mode. So, B, C, and D are correct. But the options might be multiple. Let's check the exact wording. The correct answer should be B and D. Many GATE questions state that the CPU is blocked during burst mode, making C true, but traditionally, B and D are considered the defining characteristics.

The correct order is: (Q) Complete current instruction, (P) Save process status, (T) Load new PC (jump to ISR), (R) Execute ISR, (S) Restore process status. This sequence ensures proper context saving before servicing the interrupt and correct restoration after completion.

ISRs should be short and efficient (A is true). They should NOT call blocking functions like printf(), as this can cause system instability and missed interrupts (B is false). ISRs must save and restore CPU context (C is true). Nested interrupts require enabling interrupts inside the ISR after saving context (D is true).

Parallel I/O transfers multiple bits simultaneously over multiple wires, requiring more cabling (A,B). At high speeds and longer distances, parallel signals experience skew issues, making serial I/O (transmitting bits sequentially) actually faster and more reliable for long distances (C is true). Parallel I/O is more prone to signal skew, not less (D is false).