📖 Explanation
Let's analyze each statement regarding cache and TLB:
(A) "The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address." This statement is TRUE. TLBs (Translation Lookaside Buffers) are typically implemented as associative caches, allowing simultaneous comparison of the incoming virtual page number with all entries in the TLB to find a match quickly.
(B) "If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory." This statement is TRUE. A TLB hit means that the translation from virtual address to physical address was found, and the corresponding page is present in a physical frame in main memory. Even if the data itself is not in the CPU cache (cache miss), it must reside in main memory because its page address translation was successful.
(C) "The memory access time using a given inverted page table is always same for all incoming virtual addresses." This statement is FALSE. In an inverted page table, page numbers are searched by hashing the virtual page number. If a hash collision occurs, a linked list (or similar data structure) needs to be traversed, which takes variable time depending on the length of the collision chain. Therefore, access time is not always the same for all virtual addresses.
(D) "In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same." This statement is FALSE. If two distinct virtual addresses V1 and V2 map to the same hash value (a collision), then the page table lookup will involve traversing a chain of entries at that hash location. While the overall lookup time for different addresses might vary if one has a longer chain than the other, it's not guaranteed that these specific two addresses will have different memory access times. If they both end up at the same slot and are found at the beginning of their respective chains after the initial hash, their access times could be similar. However, the more crucial point of a hashed page table is that access time is not constant for all addresses due to potential collisions and varying chain lengths. The statement says "will not be the same," which implies they must be different. It's possible for them to take the same amount of time if they are both the first entries in a collision chain, for example. The variability comes from different chain lengths, not necessarily from these two colliding addresses always taking different times.
The question asks for the statement that is FALSE. Statement (C) is definitively false because of hash collisions. Statement (D) is also false as access times for colliding entries might be the same. The solution points to C.